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ICS932S200G-T PDF预览

ICS932S200G-T

更新时间： 2024-01-06 21:02:43
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管
页数 文件大小 规格书
12页 200K
描述
Clock Generator, PDSO56

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中文翻译

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ICS932S200G-T 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：TSSOP, TSSOP56,.3,20Reach Compliance Code：unknown
风险等级：5.92JESD-30 代码：R-PDSO-G56
JESD-609代码：e0端子数量：56
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源：2.5,3.3 V
认证状态：Not Qualified子类别：Clock Generators
表面贴装：YES温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
Base Number Matches：1

ICS932S200G-T 数据手册

 浏览型号ICS932S200G-T的Datasheet PDF文件第2页浏览型号ICS932S200G-T的Datasheet PDF文件第3页浏览型号ICS932S200G-T的Datasheet PDF文件第4页浏览型号ICS932S200G-T的Datasheet PDF文件第5页浏览型号ICS932S200G-T的Datasheet PDF文件第6页浏览型号ICS932S200G-T的Datasheet PDF文件第7页 
ICS932S200  
Integrated  
Circuit  
Systems, Inc.  
Preliminary Product Preview  
Frequency Timing Generator for Dual Server/Workstation Systems  
General Description  
Features  
•
Generates the following system clocks:  
-6CPUclocks(2.5V, 100/133MHz)  
-6PCIclocks, including1freerunning(3.3V, 33MHz)  
-3IOAPICclocks(2.5V,16.67MHz)  
-2Fixedfrequency66MHzclocks(3.3V, 66MHz)  
-2REFclocks(3.3V,14.318MHz)  
The ICS932S200 is a dual CPU clock generator for  
serverworks HE-T, HE-SL-T, LE-Tchipsets for PIII type  
processors in a Dual-CPU system. Single ended CPU clocks  
provide faster than 1.5V/ns transition times by parallel  
connection of 2 CPU pins to each processor.  
Spread Spectrum may be enabled by driving the SPREAD#  
pin active. Spread spectrum typically reduces system EMI  
by 8dB to 10dB. This simplifies EMI qualification without  
resorting to board design iterations or costly shielding. The  
ICS932S200 employs a proprietary closed loop design,  
which tightly controls the percentage of spreading over  
process and temperature variations.  
-1USBclock(3.3V,48MHz)  
•
•
•
Efficient power management through PD#, CPU_STOP#  
andPCI_STOP#.  
0.5% typical down spread modulation on CPU, PCI,  
IOAPIC and 3V66 output clocks.  
Usesexternal14.318MHzcrystal.  
Key Specification:  
•
•
•
•
•
•
•
•
•
•
CPU Output Jitter: 150ps  
IOAPIC Output Jitter: 250ps  
3V66, PCIOutputJitter:250ps  
CPU Output Skew: <175ps  
PCI Output Skew: <500ps  
3V66OutputSkew<250ps  
IOAPIC Output Skew <250ps  
CPU to 3V66 Output Offset: 0 - 1.5ns (CPU leads)  
CPU to PCI Output Offset: 0 - 4.0ns (CPU leads)  
CPU toAPIC Output Offset: 1.5 - 4.0ns (CPU leads)  
Pin Configuration  
GND  
REF0  
REF1  
1
2
3
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
VDDL  
IOAPIC2  
IOAPIC1  
IOAPIC0  
GND  
VDD  
X1  
4
5
X2  
GND  
6
7
VDDL  
CPUCLK5  
CPUCLK4  
GND  
GND  
PCICLK_F  
VDD  
PCICLK0  
PCICLK1  
GND  
PCICLK2  
PCICLK3  
VDD  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
VDDL  
CPUCLK3  
CPUCLK2  
GND  
Block Diagram  
VDDL  
CPUCLK1  
CPUCLK0  
GND  
VDD  
GND  
PCI_STOP#  
CPU_STOP#  
PD#  
SPREAD#  
SEL1  
PLL2  
48MHz  
VDD  
PCICLK4  
GND  
GND  
GND  
VDD  
VDD  
X1  
X2  
XTAL  
OSC  
REF (1:0)  
2
GND  
PLL1  
Spread  
CPU  
DIVDER  
CPUCLK (5:0)  
3V66_0  
3V66_1  
VDD  
SEL0  
VDD  
48MHz  
GND  
6
Spectrum  
SEL 133/100#  
IOAPIC  
DIVDER  
IOAPIC (2:0)  
3
5
PD#  
PCI_STOP#  
CPU_STOP#  
SPREAD#  
Control  
Logic  
56-pin SSOP  
PCI  
DIVDER  
Stop  
PCICLK (4:0)  
PCICLK_F  
SEL 133/100#  
SEL0  
3V66  
DIVDER  
3V66 (1:0)  
Config.  
Reg.  
2
SEL1  
PRODUCT PREVIEW documents contain information on new  
products in the sampling or preproduction phase of development.  
Characteristic data and other specifications are subject to change  
without notice.  
932S200 RevA-7/16/01  
1234567...12

中文翻译

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