Datasheet > ICS670MI-02T

ICS670MI-02T

更新时间： 2025-08-19 19:52:35

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
7页	197K
描述
Clock Driver, CMOS, PDSO16

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技术参数
数据手册

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ICS670MI-02T 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	not_compliant	风险等级：	5.88
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e0
最大I（ol）：	0.012 A	湿度敏感等级：	1
端子数量：	16	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	3.3/5 V	认证状态：	Not Qualified
子类别：	Clock Drivers	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
Base Number Matches：	1

ICS670MI-02T 数据手册

DATASHEET

LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER

ICS670-02

Description

Features

The ICS670-02 is a high speed, low phase noise, Zero

Delay Buffer (ZDB) which integrates IDT’s proprietary

analog/digital Phase Locked Loop (PLL) techniques. Part of

• Packaged in 16-pin SOIC

• Available in Pb (lead) free package

• Clock inputs from 5 to 160 MHz (see page 2)

• Patented PLL with low phase noise

• Output clocks up to 160 MHz at 3.3 V

• 15 selectable on-chip multipliers

IDT’s ClockBlocks family, the part’s zero delay feature

means that the rising edge of the input clock aligns with the

rising edges of the outputs giving the appearance of no

delay through the device. There are two identical outputs on

the chip. The FBCLK should be used to connect to the

FBIN. Each output has its own output enable pin.

• Power down mode available

• Low phase noise: -111 dBc/Hz at 10 kHz

• Output enable function tri-states outputs

• Low jitter 15 ps one sigma

• Advanced, low power, sub-micron CMOS process

• Operating voltage of 3.3 V or 5 V

The ICS670-02 is ideal for synchronizing outputs in a large

variety of systems, from personal computers to data

communications to video. By allowing off-chip feedback

paths, the chip can eliminate the delay through other

devices. The 15 different on-chip multipliers work in a

variety of applications. For other multipliers, including

functional multipliers, see the ICS527.

• Industrial temperature range available (-40 to +85°C)

Block Diagram

VDD

OE1

Voltage

Controlled

Oscillator

ICLK

FBCLK

Phase

Detector,

Charge

Pump, and

Loop Filter

Divide by

FBIN

CLK2

S3:S0

GND

External Feedback from FBCLK is recommended.

OE2

IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 1

ICS670-02

REV G 100406

12 3 4 5 6 7

中文翻译

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与ICS670MI-02T相关器件

型号	品牌	获取价格	描述	数据表
ICS671-01	ICSI	获取价格	Zero Delay, Low Skew Buffer and Multipler
ICS671-03	ICSI	获取价格	3.3 Volt Zero Delay, Low Skew Buffer
ICS671-06	ICSI	获取价格	3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
ICS671-15	ICSI	获取价格	ZERO DELAY, LOW SKEW BUFFER
ICS671G-05ILF	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, 0.6
ICS671G-05ILFT	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, 0.6
ICS671G-06ILF	IDT	获取价格	PLL Based Clock Driver, 671 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
ICS671G-06ILFT	IDT	获取价格	PLL Based Clock Driver, 671 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
ICS671G-15	ICSI	获取价格	ZERO DELAY, LOW SKEW BUFFER
ICS671G-15T	ICSI	获取价格	ZERO DELAY, LOW SKEW BUFFER

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