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IC41C8512-50K

更新时间： 2024-01-12 05:24:16

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
21页	226K
描述
512K x 8 bit Dynamic RAM with EDO Page Mode

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IC41C8512-50K 数据手册

IC41C8512

IC41LV8512

ELECTRICAL CHARACTERISTICS⁽¹⁾

(Recommended Operating Conditions unless otherwise noted.)

Symbol Parameter

Test Condition

Speed Min. Max.

Unit

I^IL

Input Leakage Current

Any input 0V ≤ VIN ≤ Vcc

–10

µA

Other inputs not under test = 0V

IIO

Output Leakage Current

Output is disabled (Hi-Z)

–10

µA

0V ≤ VOUT ≤ Vcc

VOH

VOL

ICC1

Output High Voltage Level

Output Low Voltage Level

Standby Current: TTL

IOH = –2.5 mA

IOL =+2.1mA

2.4

—

0.4

RAS, CAS ≥ VIH

3.3V

—

0.5

ICC2

I^CC3

Standby Current: CMOS

RAS, CAS ≥ VCC – 0.2V

3.3V

—

0.5

OperatingCurrent:

RAS, CAS,

Address Cycling, tRC = tRC (min.)

-35

-50

-60

—

120

110

100

RandomRead/Write^(2,3,4)

Average Power Supply Current

ICC4

ICC5

ICC6

OperatingCurrent:

RAS = VIL, CAS,

-35

-50

-60

—

100

EDO Page Mode^(2,3,4)

Cycling tPC = tPC (min.)

Average Power Supply Current

Refresh Current:

RAS Cycling, CAS ≥ VIH

tRC = tRC (min.)

-35

-50

-60

—

120

110

100

RAS-Only^(2,3)

Average Power Supply Current

Refresh Current:

RAS, CAS Cycling

tRC = tRC (min.)

-35

-50

-60

—

120

110

100

CBR^(2,3,5)

Average Power Supply Current

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device

operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.

2. Dependent on cycle rates.

3. Specified values are obtained with minimum cycle time and the output open.

4. Column-address is changed once each EDO page cycle.

5. Enables on-chip refresh and address counters.

Integrated Circuit Solution Inc.

DR029-0A 09/28/2001

1...4 5 678 9 10...21

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