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IC41C44004-60JI PDF预览

IC41C44004-60JI

更新时间: 2024-02-03 15:43:05
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
20页 235K
描述
4Mx4 bit Dynamic RAM with EDO Page Mode

IC41C44004-60JI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:TSOP2-26/24Reach Compliance Code:compliant
风险等级:5.92访问模式:EDO PAGE
最长访问时间:60 ns其他特性:RAS ONLY CAS BEFORE RAS /HIDDEN REFRESH
I/O 类型:COMMONJESD-30 代码:R-PDSO-G24
JESD-609代码:e0内存密度:16777216 bit
内存集成电路类型:EDO DRAM内存宽度:4
功能数量:1端口数量:1
端子数量:24字数:4194304 words
字数代码:4000000最高工作温度:85 °C
最低工作温度:-40 °C组织:4MX4
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP封装等效代码:TSOP24/26,.36
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
认证状态:Not Qualified刷新周期:4096
反向引出线:NO自我刷新:NO
最大待机电流:0.001 A最大压摆率:0.11 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子位置:DUAL

IC41C44004-60JI 数据手册

 浏览型号IC41C44004-60JI的Datasheet PDF文件第4页浏览型号IC41C44004-60JI的Datasheet PDF文件第5页浏览型号IC41C44004-60JI的Datasheet PDF文件第6页浏览型号IC41C44004-60JI的Datasheet PDF文件第8页浏览型号IC41C44004-60JI的Datasheet PDF文件第9页浏览型号IC41C44004-60JI的Datasheet PDF文件第10页 
IC41C4400x and IC41LV4400x Series  
AC CHARACTERISTICS(1,2,3,4,5,6)  
(Recommended Operating Conditions unless otherwise noted.)  
-50  
Min. Max.  
-60  
Min. Max.  
Symbol  
Parameter  
Units  
tRC  
Random READ or WRITE Cycle Time  
84  
50  
13  
25  
10K  
104  
60  
15  
30  
10K  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(6, 7)  
tRAC  
tCAC  
tAA  
Access Time from RAS  
50  
30  
8
60  
40  
10  
9
(6, 8, 15)  
Access Time from CAS  
Access Time from Column-Address(6)  
RAS Pulse Width  
tRAS  
tRP  
RAS Precharge Time  
tCAS  
tCP  
CAS Pulse Width(23)  
10K  
10K  
CAS Precharge Time(9)  
CAS Hold Time (21)  
9
37  
45  
tCSH  
tRCD  
tASR  
tRAH  
tASC  
tCAH  
tAR  
38  
12  
0
40  
14  
0
RAS to CAS Delay Time(10, 20)  
Row-Address Setup Time  
Row-Address Hold Time  
Column-Address Setup Time(20)  
Column-Address Hold Time(20)  
8
10  
0
0
8
10  
40  
Column-Address Hold Time  
(referenced to RAS)  
30  
tRAD  
tRAL  
tRPC  
tRSH  
tRHCP  
tCLZ  
tCRP  
tOD  
RAS to Column-Address Delay Time(11)  
Column-Address to RAS Lead Time  
RAS to CAS Precharge Time  
RAS Hold Time  
10  
25  
5
25  
15  
12  
12  
30  
5
30  
15  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
8
10  
35  
0
RAS Hold Time from CAS Precharge  
CAS to Output in Low-Z(15, 24)  
CAS to RAS Precharge Time(21)  
Output Disable Time(19, 24)  
30  
0
5
5
3
3
tOE  
Output Enable Time(15, 16)  
12  
15  
tOED  
tOEHC  
tOEP  
tOES  
tRCS  
tRRH  
Output Enable Data Delay (Write)  
OE HIGH Hold Time from CAS HIGH  
OE HIGH Pulse Width  
5
5
10  
5
10  
5
OE LOW to CAS HIGH Setup Time  
Read Command Setup Time(17, 20)  
0
0
Read Command Hold Time  
0
0
(referenced to RAS)(12)  
tRCH  
Read Command Hold Time  
0
0
ns  
(referenced to CAS)(12, 17, 21)  
tWCH  
tWCR  
Write Command Hold Time(17)  
8
10  
50  
ns  
ns  
Write Command Hold Time  
40  
(referenced to RAS)(17)  
tWP  
Write Command Pulse Width(17)  
8
7
10  
7
ns  
ns  
ns  
ns  
ns  
ns  
tWPZ  
tRWL  
tCWL  
tWCS  
tDHR  
WE Pulse Widths to Disable Outputs  
Write Command to RAS Lead Time(17)  
Write Command to CAS Lead Time(17, 21)  
Write Command Setup Time(14, 17, 20)  
Data-in Hold Time (referenced to RAS)  
13  
8
15  
10  
0
0
39  
39  
Integrated Circuit Solution Inc.  
DR007-0B 10/17/2002  
7

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