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IC41C44004-60JI PDF预览

IC41C44004-60JI

更新时间: 2024-02-26 11:40:35
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
20页 235K
描述
4Mx4 bit Dynamic RAM with EDO Page Mode

IC41C44004-60JI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:TSOP2-26/24Reach Compliance Code:compliant
风险等级:5.92访问模式:EDO PAGE
最长访问时间:60 ns其他特性:RAS ONLY CAS BEFORE RAS /HIDDEN REFRESH
I/O 类型:COMMONJESD-30 代码:R-PDSO-G24
JESD-609代码:e0内存密度:16777216 bit
内存集成电路类型:EDO DRAM内存宽度:4
功能数量:1端口数量:1
端子数量:24字数:4194304 words
字数代码:4000000最高工作温度:85 °C
最低工作温度:-40 °C组织:4MX4
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP封装等效代码:TSOP24/26,.36
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
认证状态:Not Qualified刷新周期:4096
反向引出线:NO自我刷新:NO
最大待机电流:0.001 A最大压摆率:0.11 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子位置:DUAL

IC41C44004-60JI 数据手册

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IC41C4400x and IC41LV4400x Series  
ELECTRICAL CHARACTERISTICS(1)  
(Recommended Operating Conditions unless otherwise noted.)  
Symbol Parameter  
Test Condition  
Speed Min. Max.  
Unit  
IIL  
Input Leakage Current  
Any input 0V < VIN < Vcc  
Other inputs not under test = 0V  
5  
5  
2.4  
5
µA  
IIO  
Output Leakage Current  
Output High Voltage Level  
Output Low Voltage Level  
Standby Current: TTL  
Output is disabled (Hi-Z)  
0V < VOUT < Vcc  
5
µA  
V
VOH  
VOL  
ICC1  
ICC2  
ICC3  
IOH = 5.0 mA with VCC=5V  
IOH = 2.0 mA with VCC=3.3V  
IOL = 4.2 mA with VCC=5V  
IOL = 2 mA with VCC=3.3V  
0.4  
V
RAS, CAS VIH  
5V  
3.3V  
2
0.5  
mA  
mA  
mA  
Standby Current: CMOS  
RAS, CAS > VCC 0.2V  
5V  
3.3V  
1
0.5  
Operating Current:  
RAS, CAS,  
Address Cycling, tRC = tRC (min.)  
-50  
-60  
120  
110  
Random Read/Write(2,3,4)  
Average Power Supply Current  
ICC4  
ICC5  
ICC6  
Operating Current:  
RAS = VIL, CAS,  
-50  
-60  
90  
80  
mA  
mA  
mA  
EDO Page Mode(2,3,4)  
Cycling tPC = tPC (min.)  
Average Power Supply Current  
Refresh Current:  
RAS Cycling, CAS > VIH  
tRC = tRC (min.)  
-50  
-60  
120  
110  
RAS-Only(2,3)  
Average Power Supply Current  
Refresh Current:  
RAS, CAS Cycling  
tRC = tRC (min.)  
-50  
-60  
120  
110  
CBR(2,3,5)  
Average Power Supply Current  
Notes:  
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device  
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.  
2. Dependent on cycle rates.  
3. Specified values are obtained with minimum cycle time and the output open.  
4. Column-address is changed once each EDO page cycle.  
5. Enables on-chip refresh and address counters.  
6
Integrated Circuit Solution Inc.  
DR007-0B 10/17/2002  

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