Datasheet > IC41C44004-60J

IC41C44004-60J

更新时间： 2024-01-26 16:46:15

品牌	Logo	应用领域
美国芯成 - ISSI		动态存储器光电二极管内存集成电路
页数	文件大小	规格书
20页	196K
描述
EDO DRAM, 4MX4, 60ns, CMOS, PDSO24,

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技术参数
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IC41C44004-60J 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	SOJ-26/24	Reach Compliance Code：	compliant
风险等级：	5.83	访问模式：	EDO PAGE
最长访问时间：	60 ns	其他特性：	RAS ONLY CAS BEFORE RAS /HIDDEN REFRESH
I/O 类型：	COMMON	JESD-30 代码：	R-PDSO-J24
JESD-609代码：	e0	内存密度：	16777216 bit
内存集成电路类型：	EDO DRAM	内存宽度：	4
功能数量：	1	端口数量：	1
端子数量：	24	字数：	4194304 words
字数代码：	4000000	最高工作温度：	70 °C
最低工作温度：		组织：	4MX4
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOJ	封装等效代码：	SOJ24/26,.34
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
认证状态：	Not Qualified	刷新周期：	4096
反向引出线：	NO	自我刷新：	NO
最大待机电流：	0.001 A	最大压摆率：	0.11 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子位置：	DUAL	Base Number Matches：	1

IC41C44004-60J 数据手册

IC41C4400x and IC41LV4400x Series

FunctionalDescription

Refresh Cycle

The IC41C4400x and IC41LV4400x are CMOS DRAMs

optimized for high-speed bandwidth, low power

applications. During READ or WRITE cycles, each bit is

uniquely addressed through the 11 or 12 address bits.

These are entered 11 bits (A0-A10) at a time for the 2K

refresh device or 12 bits (A0-A11) at a time for the 4K

refresh device. The row address is latched by the Row

Address Strobe (RAS). The column address is latched by

the Column Address Strobe (CAS). RAS is used to latch

the first nine bits and CAS is used the latter ten bits.

To retain data, 2,048 refresh cycles are required in each

32 ms period, or 4,096 refresh cycles are required in each

64ms period. There are two ways to refresh the memory:

1. By clocking each of the 2,048 row addresses (A0

through A10) or 4096 row addresses (A0 through A11)

with RAS at least once every 32 ms or 64ms respectively.

Any read, write, read-modify-write or RAS-only cycle

refreshes the addressed row.

2. Using a CAS-before-RAS refresh cycle. CAS-before-

RAS refresh is activated by the falling edge of RAS,

while holding CAS LOW. In CAS-before-RAS refresh

cycle, an internal 9-bit counter provides the row ad-

dresses and the external address inputs are ignored.

Memory Cycle

A memory cycle is initiated by bring RAS LOW and it is

terminated by returning both RAS and CAS HIGH. To

ensures proper device operation and data integrity any

memory cycle, once initiated, must not be ended or

aborted before the minimum t^RAStime has expired. A new

cycle must not be initiated until the minimum precharge

time t^RP, tCP has elapsed.

CAS-before-RAS is a refresh-only mode and no data

access or device selection is allowed. Thus, the output

remains in the High-Z state during the cycle.

Power-On

Read Cycle

After application of the VCC supply, an initial pause of

200 µs is required followed by a minimum of eight initial-

ization cycles (any combination of cycles containing a

RAS signal).

A read cycle is initiated by the falling edge of CAS or OE,

whichever occurs last, while holding WE HIGH. The

column address must be held for a minimum time specified

by t^AR. Data Out becomes valid only when tRAC, tAA, tCAC

and tOEA are all satisfied. As a result, the access time is

dependent on the timing relationships between these

parameters.

During power-on, it is recommended that RAS track with

V^CCor be held at a valid VIH to avoid current surges.

Write Cycle

A write cycle is initiated by the falling edge of CAS and WE,

whichever occurs last. The input data must be valid at or

before the falling edge of CAS or WE, whichever occurs

last.

Integrated Circuit Solution Inc.

DR007-0B 10/17/2002

1 2 345 6 7...20

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与IC41C44004-60J相关器件

型号	品牌	描述	获取价格	数据表
IC41C44004-60JI	ICSI	4Mx4 bit Dynamic RAM with EDO Page Mode	获取价格
IC41C44004-60T	ICSI	4Mx4 bit Dynamic RAM with EDO Page Mode	获取价格
IC41C44004-60T	ISSI	EDO DRAM, 4MX4, 60ns, CMOS, PDSO24	获取价格
IC41C44004-60TI	ICSI	4Mx4 bit Dynamic RAM with EDO Page Mode	获取价格
IC41C4400X	ICSI	4Mx4 bit Dynamic RAM with EDO Page Mode	获取价格
IC41C44052-50J	ISSI	Fast Page DRAM, 4MX4, 50ns, CMOS, PDSO24,	获取价格

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