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IC41C16100S-45KI PDF预览

IC41C16100S-45KI

更新时间: 2024-02-28 18:58:00
品牌 Logo 应用领域
美国芯成 - ISSI 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
21页 663K
描述
EDO DRAM, 1MX16, 45ns, CMOS, PDSO42, 0.400 INCH, SOJ-42

IC41C16100S-45KI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:0.400 INCH, SOJ-42Reach Compliance Code:compliant
风险等级:5.83访问模式:EDO PAGE
最长访问时间:45 ns其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH/SELF REFRESH
I/O 类型:COMMONJESD-30 代码:R-PDSO-J42
JESD-609代码:e0内存密度:16777216 bit
内存集成电路类型:EDO DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:42字数:1048576 words
字数代码:1000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:1MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ42,.44封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:5 V
认证状态:Not Qualified刷新周期:1024
自我刷新:YES最大待机电流:0.001 A
子类别:DRAMs最大压摆率:0.19 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

IC41C16100S-45KI 数据手册

 浏览型号IC41C16100S-45KI的Datasheet PDF文件第1页浏览型号IC41C16100S-45KI的Datasheet PDF文件第2页浏览型号IC41C16100S-45KI的Datasheet PDF文件第3页浏览型号IC41C16100S-45KI的Datasheet PDF文件第5页浏览型号IC41C16100S-45KI的Datasheet PDF文件第6页浏览型号IC41C16100S-45KI的Datasheet PDF文件第7页 
IC41C16100S  
IC41LV16100S  
TRUTH TABLE  
Function  
RAS  
LCAS UCAS  
WE  
X
OE  
X
Address tR/tC I/O  
Standby  
Read: Word  
Read: Lower Byte  
H
L
L
H
L
L
H
L
H
X
High-Z  
H
L
ROW/COL  
ROW/COL  
DOUT  
H
L
Lower Byte, DOUT  
Upper Byte, High-Z  
Read: Upper Byte  
L
H
L
H
L
ROW/COL  
Lower Byte, High-Z  
Upper Byte, DOUT  
Write: Word (Early Write)  
Write: Lower Byte (Early Write)  
L
L
L
L
L
H
L
L
X
X
ROW/COL  
ROW/COL  
DIN  
Lower Byte, DIN  
Upper Byte, High-Z  
Write: Upper Byte (Early Write)  
Read-Write(1,2)  
L
L
H
L
L
L
L
X
ROW/COL  
ROW/COL  
Lower Byte, High-Z  
Upper Byte, DIN  
H
L
L
H
DOUT, DIN  
EDO Page-Mode Read(2) 1st Cycle:  
2nd Cycle:  
L
L
L
H
L
L
H
L
L
H
H
H
L
L
L
ROW/COL  
NA/COL  
NA/NA  
DOUT  
DOUT  
DOUT  
H
H
Any Cycle:  
L
H
L
H
EDO Page-Mode Write(1) 1st Cycle:  
2nd Cycle:  
L
H
L
H
L
L
X
ROW/COL  
DIN  
L
H
L
H
L
L
X
NA/COL  
DIN  
EDO Page-Mode(1,2)  
Read-Write  
1st Cycle:  
L
L
H
L
H
L
H
L
L
L
H
H
ROW/COL  
NA/COL  
DOUT, DIN  
DOUT, DIN  
2nd Cycle:  
H
L
H
L
H
L
Hidden Refresh  
Read(2)  
L
H
L
L
L
L
H
L
L
L
H
L
H
L
X
X
L
ROW/COL  
DOUT  
Write(1,3)  
L
H
X
ROW/COL  
DOUT  
RAS-Only Refresh  
L
X
X
ROW/NA  
X
High-Z  
High-Z  
CBR Refresh(4)  
H
L
Notes:  
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).  
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).  
3. EARLY WRITE only.  
4. At least one of the two CAS signals must be active (LCAS or UCAS).  
4
Integrated Circuit Solution Inc.  
DR010-0D 11/26/2004  

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