5秒后页面跳转
IBM04364BSLAD-7(D) PDF预览

IBM04364BSLAD-7(D)

更新时间: 2024-02-08 04:57:31
品牌 Logo 应用领域
国际商业机器公司 - IBM 静态存储器
页数 文件大小 规格书
21页 464K
描述
Standard SRAM, 128KX36, 3.5ns, CMOS, PBGA119, BGA-119

IBM04364BSLAD-7(D) 技术参数

生命周期:Contact Manufacturer零件包装代码:BGA
包装说明:BGA,针数:119
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.76
Base Number Matches:1

IBM04364BSLAD-7(D) 数据手册

 浏览型号IBM04364BSLAD-7(D)的Datasheet PDF文件第1页浏览型号IBM04364BSLAD-7(D)的Datasheet PDF文件第2页浏览型号IBM04364BSLAD-7(D)的Datasheet PDF文件第3页浏览型号IBM04364BSLAD-7(D)的Datasheet PDF文件第5页浏览型号IBM04364BSLAD-7(D)的Datasheet PDF文件第6页浏览型号IBM04364BSLAD-7(D)的Datasheet PDF文件第7页 
IBM04184BSLAD  
IBM04364BSLAD  
256K x 18 & 128K x 36 SW SRAM  
Preliminary  
SRAM Features  
Standard Write  
In Standard Write function, write data must be registered in the same cycle as addresses and controls.  
Mode Control  
Mode control pins: M1 and M2 are used to select four different JEDEC standard read protocols. This SRAM  
only supports the single clock pipeline (M1 = V , M2 = V ) protocol. Mode control inputs must be set with  
SS  
DD  
power up and must not change during SRAM operation.  
Power Down Mode  
Power Down Mode, or “Sleep Mode” is accomplished by switching asynchronous signal ZZ high. When pow-  
ering the SRAM down inputs must be dropped first and V must be dropped before or simultaneously with  
DDQ  
V
.
DD  
Power-Up Requirements  
In order to guarantee the optimum internally regulated supply voltage, the SRAM requires 4 µs of power-up  
time after V reaches its operating range. Power up requirements for the SRAM are that Vdd must be pow-  
DD  
ered before or simultaneously with V  
, then inputs after V  
. V  
limitation is that V  
should not  
DDQ  
DDQ  
DDQ  
DDQ  
exceed V supply by more than 0.4V during power up.  
DD  
Sleep Mode Operation  
Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin HIGH. During sleep mode, all  
other inputs are ignored and outputs are brought to a High-Z state. Sleep mode current and output High Z are  
guaranteed after the specified sleep mode enable time. During sleep mode, the array data contents are pre-  
served. Sleep mode must not be initiated until after all pending operations have completed, as any pending  
operation is not guaranteed to properly complete after sleep mode is initiated. Sense amp data is lost. Normal  
operation can be resumed by bringing ZZ low, but only after specified sleep mode recovery time.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
75H4340  
Revised 2/99  
Page 4 of 21  

与IBM04364BSLAD-7(D)相关器件

型号 品牌 描述 获取价格 数据表
IBM04368CBLBC-28 IBM Standard SRAM, 256KX36, 1.8ns, CMOS, PBGA153, BGA-153

获取价格

IBM0436A11NLAA-3N IBM Standard SRAM, 32KX36, 2ns, CMOS, PBGA119, BGA-119

获取价格

IBM0436A11NLAA-4 IBM Standard SRAM, 32KX36, 2.25ns, CMOS, PBGA119, BGA-119

获取价格

IBM0436A11NLAA-5 IBM Standard SRAM, 32KX36, 2.5ns, CMOS, PBGA119, BGA-119

获取价格

IBM0436A41DLAB-3 ETC SYNC SRAM|128KX36|CMOS|BGA|119PIN|PLASTIC

获取价格

IBM0436A41DLAB-3F ETC x36 Fast Synchronous SRAM

获取价格