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IBM041812PQKB-9 PDF预览

IBM041812PQKB-9

更新时间: 2024-01-11 19:35:17
品牌 Logo 应用领域
国际商业机器公司 - IBM 静态存储器内存集成电路
页数 文件大小 规格书
14页 218K
描述
Standard SRAM, 64KX18, 9ns, CMOS, PQFP100, TQFP-100

IBM041812PQKB-9 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LQFP, QFP100,.63X.87
针数:100Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.89最长访问时间:9 ns
I/O 类型:COMMONJESD-30 代码:R-PQFP-G100
JESD-609代码:e0长度:20 mm
内存密度:1179648 bit内存集成电路类型:STANDARD SRAM
内存宽度:18功能数量:1
端子数量:100字数:65536 words
字数代码:64000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX18输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP100,.63X.87封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.025 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.3 mA
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

IBM041812PQKB-9 数据手册

 浏览型号IBM041812PQKB-9的Datasheet PDF文件第1页浏览型号IBM041812PQKB-9的Datasheet PDF文件第2页浏览型号IBM041812PQKB-9的Datasheet PDF文件第3页浏览型号IBM041812PQKB-9的Datasheet PDF文件第5页浏览型号IBM041812PQKB-9的Datasheet PDF文件第6页浏览型号IBM041812PQKB-9的Datasheet PDF文件第7页 
IBM041812PQKB  
64K X 18 BURST SRAM  
Preliminary  
Burst SRAM Clock Truth Table  
CLK  
CS2  
H
CS2  
X
CS  
L
ADSP  
ADSC  
ADV  
X
WE  
X
OE  
X
DQ  
Operation  
LH  
LH  
LH  
LH  
L
L
X
X
L
L
High-Z Deselected Cycle  
High-Z Deselected Cycle  
High-Z Deselected Cycle  
High-Z Deselected Cycle  
X
L
L
X
X
X
H
X
X
X
X
X
X
X
X
L
X
X
X
X
Read from External  
Q
LH  
LH  
LH  
LH  
LH  
LH  
LH  
L
L
L
L
X
X
X
H
H
H
H
X
X
X
L
L
L
L
X
X
X
L
L
X
X
L
X
X
X
X
L
X
X
H
L
L
H
L
Address, Begin Burst  
Read from External  
High-Z  
Address, Begin Burst  
Read from External  
Q
H
H
H
H
H
Address, Begin Burst  
Write to External  
D
L
X
L
Address, Begin Burst  
Read from next Add.,  
Continue Burst  
H
H
H
H
L
Q
Write to next Add.,  
Continue Burst  
L
X
L
D
Read from Current  
Q
H
H
Add., Suspend Burst  
Write to Current Add.,  
LH  
LH  
LH  
X
X
X
X
X
X
X
H
H
H
X
X
H
L
H
X
L
L
X
H
X
X
L
D
Suspend Burst  
High-Z Deselect Cycle  
Read from next Add.,  
Continue Burst  
H
Q
Write to next Add.,  
LH  
LH  
LH  
X
X
X
X
X
X
H
H
H
X
X
X
H
H
H
L
H
H
L
H
L
X
L
D
Continue Burst  
Read from current  
Q
Add., Suspend Burst  
Write to current Add.,  
Suspend Burst  
X
D
1. For a write operation preceded by a read cycle, OE must be HIGH early enough to allow Input Data Setup, and must be kept HIGH  
through Input Data Hold Time.  
2. WE refers to WEa, WEb.  
3. ADSP is gated by CS, and CS is used to block ADSP when CS = VIH, as required in applications using Processor Address Pipelin-  
ing.  
4. All Addresses, Data In and Control signals are registered on the rising edge of CLK.  
Burst Sequence Truth Table  
(A1,A0)  
External Address  
A15-A2  
Notes  
(0,0)  
(0,0)  
(0,1)  
(1,0)  
(1,1)  
(0,1)  
(0,1)  
(0,0)  
(1,1)  
(1,0)  
(1,0)  
(1,0)  
(1,1)  
(0,0)  
(0,1)  
(1,1)  
(1,1)  
(1,0)  
(0,1)  
(0,0)  
1st Access  
2nd Access  
3rd Access  
4th Access  
A15-A2  
A15-A2  
A15-A2  
A15-A2  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
26H4672  
SA14-4663-01  
Revised 9/97  
Page 4 of 14  

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