Datasheet > HY5W26DF-H

HY5W26DF-H

更新时间： 2024-02-26 04:15:53

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器内存集成电路
页数	文件大小	规格书
13页	259K
描述
Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 0.80 MM PITCH, FBGA-54

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HY5W26DF-H 技术参数

生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	TFBGA,	针数：	54
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.02	风险等级：	5.71
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	5.4 ns
其他特性：	AUTO/SELF REFRESH	JESD-30 代码：	S-PBGA-B54
JESD-609代码：	e1	长度：	8 mm
内存密度：	134217728 bit	内存集成电路类型：	SYNCHRONOUS DRAM
内存宽度：	16	功能数量：	1
端口数量：	1	端子数量：	54
字数：	8388608 words	字数代码：	8000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	8MX16
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, THIN PROFILE, FINE PITCH
认证状态：	Not Qualified	座面最大高度：	1.2 mm
自我刷新：	YES	最大供电电压 (Vsup)：	2.7 V
最小供电电压 (Vsup)：	2.3 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN SILVER COPPER
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	宽度：	8 mm
Base Number Matches：	1

HY5W26DF-H 数据手册

Preliminary

HY5W26D(L)F(P)-H

4Banks x 2M x 16bits Synchronous DRAM

DESCRIPTION

The Hynix HY5W26D(L)F(P)-H is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applica-

tions which require wide data I/O and high bandwidth. HY5W26D(L)F(P)-H is organized as 4banks of 2,097,152x16.

HY5W26D(L)F(P)-H is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and

outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve

very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write

cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-

quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or

can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-

stricted by a '2N' rule)

FEATURES

•

Voltage : VDD, VDDQ 2.5V supply voltage

All device pins are compatible with LVTTL interface

54Ball FBGA

•

Auto refresh and self refresh

4096 Refresh cycles / 64ms

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

Programmable CAS Latency ; 2, 3 Clocks

Burst Read Single Write operation

All inputs and outputs referenced to positive edge of

system clock

•

Data mask function by UDQM, LDQM

Internal four banks operation

•

ORDERING INFORMATION

Clock

CAS

Latency

Part No.

Power

Organization

Package

Frequency

HY5W26DF-H

54Ball FBGA, Lead

Normal

HY5W26DFP-H

HY5W26DLF-H

HY5W26DLFP-H

54Ball FBGA, Lead Free

54Ball FBGA, Lead

4Banks x 2Mbits

x16

133MHz

Low

power

54Ball FBGA, Lead Free

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev. 0.2 / Apr. 2004

123 4 5 6 7...13

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与HY5W26DF-H相关器件

型号	品牌	描述	获取价格	数据表
HY5W26DLF-H	HYNIX	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 0.80 MM PITCH, FBGA-54	获取价格
HY5W26DLFP-H	HYNIX	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 0.80 MM PITCH, LEAD FREE, FBGA-54	获取价格
HY5W2A2(L/S)F	ETC	4Mx32\|2.5V\|4K\|H\|Handy SDRAM - 128M	获取价格
HY5W2A2(L/S)FC	ETC	4Mx32\|2.5V\|4K\|H\|Handy SDRAM - 128M	获取价格
HY5W2A2F-HC	HYNIX	Synchronous DRAM, 4MX32, 5.4ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90	获取价格
HY5W2A2F-P	HYNIX	Synchronous DRAM, 4MX32, 7ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90	获取价格

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