Datasheet > HY5V52ALFP-HI

HY5V52ALFP-HI

更新时间： 2024-01-24 12:48:41

品牌	Logo	应用领域
海力士 - HYNIX		时钟动态存储器内存集成电路
页数	文件大小	规格书
47页	677K
描述
Synchronous DRAM, 8MX32, 5.4ns, CMOS, PBGA90

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HY5V52ALFP-HI 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	FBGA, BGA90,9X15,32	Reach Compliance Code：	unknown
风险等级：	5.84	最长访问时间：	5.4 ns
最大时钟频率 (fCLK)：	133 MHz	I/O 类型：	COMMON
交错的突发长度：	1,2,4,8	JESD-30 代码：	R-PBGA-B90
内存密度：	268435456 bit	内存集成电路类型：	SYNCHRONOUS DRAM
内存宽度：	32	端子数量：	90
字数：	8388608 words	字数代码：	8000000
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	8MX32	封装主体材料：	PLASTIC/EPOXY
封装代码：	FBGA	封装等效代码：	BGA90,9X15,32
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, FINE PITCH
电源：	3.3 V	认证状态：	Not Qualified
刷新周期：	4096	连续突发长度：	1,2,4,8,FP
最大待机电流：	0.001 A	子类别：	DRAMs
最大压摆率：	0.22 mA	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	BALL
端子节距：	0.8 mm	端子位置：	BOTTOM
Base Number Matches：	1

HY5V52ALFP-HI 数据手册

111

Synchronous DRAM Memory 256Mbit

HY5V52A(L)F(P)-xxI Series

DESCRIPTION

The Hynix Synchronous DRAM is suited for advaced-consumer application which use the batteries such as Image dis-

player application (Digital still camera etc.) and portable applications (portable multimedia player and portable audio

player). Also, Hynix SDRAMs is used high-speed consumer applications. Short for Hynix Synchronous DRAM, a type of

DRAM that can run at much higher clock speeds and Low power consumption memory.

The Hynix HY5V52ALF(P) Synchronous DRAM is 268,435,456bit CMOS Synchronous DRAM, ideally suited for the con-

sumer memory applications which requires large memory density and high bandwidth. It is organized as 4banks of

2,097,152 x 32I/O.

Synchronous DRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Synchronous

DRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization

with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x32

Input/ Output bus. All the commands are latched in synchronization with the rising edge of CLK.

The Synchronous DRAM provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4,

8 locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is

initiated at the end of the burst access. The Synchronous DRAM uses an internal pipelined architecture to achieve

high-speed operation. This architecture is compartible with the 2n rule of prefetch architectures, but it also allows the

column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one

bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed,

randon-access operation.

Read and write accesses to the Hynix Synchronous DRAM are burst oriented;

accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.

The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be

accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and

the starting column location for the burst access.

A burst of Read or Write cycles in progress can be terminated by a burst terminate command or can be interrupted

and replaced by a new burst Read or Write command on any cycle(This pipelined design is not restricted by a 2N rule).

All inputs are LVTTL compatible. Devices will have a VDD and VDDQ supply of 3.3V (nominal).

Rev 1.0 / Dec. 2007

1 234 5 6 7...47

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与HY5V52ALFP-HI相关器件

型号	品牌	描述	获取价格	数据表
HY5V52CF	ETC	8Mx32\|3.3V\|8K\|H/8/P/S\|SDR SDRAM - 256M	获取价格
HY5V52CF-P	HYNIX	Synchronous DRAM, 8MX32, 6ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90	获取价格
HY5V52CF-S	HYNIX	Synchronous DRAM, 8MX32, 6ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90	获取价格
HY5V52CLF-H	HYNIX	Synchronous DRAM, 8MX32, 5.5ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90	获取价格
HY5V52ELM-6	HYNIX	Synchronous DRAM, 8MX32, 5.4ns, CMOS, PBGA90, 8 X 13 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, FB	获取价格
HY5V52ELM-6I	HYNIX	Synchronous DRAM, 8MX32, 5.4ns, CMOS, PBGA90, 8 X 13 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, FB	获取价格

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