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HY5V22LF-55I PDF预览

HY5V22LF-55I

更新时间： 2024-11-27 20:56:43
品牌 Logo 应用领域
海力士 - HYNIX 时钟动态存储器内存集成电路
页数 文件大小 规格书
14页 292K
描述
Synchronous DRAM, 4MX32, 5ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90

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HY5V22LF-55I 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：TFBGA, BGA90,9X15,32
针数：90Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.32.00.02
风险等级：5.92访问模式：FOUR BANK PAGE BURST
最长访问时间：5 ns其他特性：AUTO/SELF REFRESH
最大时钟频率 (fCLK)：183 MHzI/O 类型：COMMON
交错的突发长度：1,2,4,8JESD-30 代码：R-PBGA-B90
长度：13 mm内存密度：134217728 bit
内存集成电路类型：SYNCHRONOUS DRAM内存宽度：32
功能数量：1端口数量：1
端子数量：90字数：4194304 words
字数代码：4000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：4MX32输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TFBGA
封装等效代码：BGA90,9X15,32封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
刷新周期：4096座面最大高度：1.2 mm
自我刷新：YES连续突发长度：1,2,4,8,FP
最大待机电流：0.001 A子类别：DRAMs
最大压摆率：0.22 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：8 mm
Base Number Matches：1

HY5V22LF-55I 数据手册

 浏览型号HY5V22LF-55I的Datasheet PDF文件第2页浏览型号HY5V22LF-55I的Datasheet PDF文件第3页浏览型号HY5V22LF-55I的Datasheet PDF文件第4页浏览型号HY5V22LF-55I的Datasheet PDF文件第5页浏览型号HY5V22LF-55I的Datasheet PDF文件第6页浏览型号HY5V22LF-55I的Datasheet PDF文件第7页 
HY57V283220T-I/ HY5V22F-I  
4 Banks x 1M x 32Bit Synchronous DRAM  
DESCRIPTION  
The Hynix HY57V283220T-I / HY5V22F-I is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the mem-  
ory applications which require wide data I/O and high bandwidth. HY57V283220T-I / HY5V22F-I is organized as  
4banks of 1,048,576x32.  
HY57V283220T-I / HY5V22F-I is offering fully synchronous operation referenced to a positive edge of the clock. All  
inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to  
achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.  
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write  
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count  
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate  
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined  
design is not restricted by a `2N` rule.)  
FEATURES  
•
•
•
•
JEDEC standard 3.3V power supply  
•
•
•
Auto refresh and self refresh  
All device pins are compatible with LVTTL interface  
86TSOP-II, 90Ball FBGA with 0.8mm of pin pitch  
4096 refresh cycles / 64ms  
Programmable Burst Length and Burst Type  
- 1, 2, 4, 8 or full page for Sequential Burst  
- 1, 2, 4 or 8 for Interleave Burst  
All inputs and outputs referenced to positive edge of  
system clock  
•
•
Data mask function by DQM0,1,2 and 3  
Internal four banks operation  
•
•
Programmable CAS Latency ; 2, 3 Clocks  
Burst Read Single Write operation  
ORDERING INFORMATION  
Part No.  
Clock Frequency  
Organization  
Interface  
Package  
HY57V283220(L)T-5I  
HY5V22(L)F-5I  
4Banks x 1Mbits  
x32  
86TSOP-II  
200MHz  
183MHz  
166MHz  
143MHz  
125MHz  
100MHz  
100MHz  
LVTTL  
90Ball FBGA  
HY57V283220(L)T-55I  
HY5V22(L)F-55I  
4Banks x 1Mbits  
x32  
86TSOP-II  
90Ball FBGA  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
HY57V283220(L)T-6I  
HY5V22(L)F-6I  
4Banks x 1Mbits  
x32  
86TSOP-II  
90Ball FBGA  
HY57V283220(L)T-7I  
HY5V22(L)F-7I  
4Banks x 1Mbits  
x32  
86TSOP-II  
90Ball FBGA  
HY57V283220(L)T-8I  
HY5V22(L)F-8I  
4Banks x 1Mbits  
x32  
86TSOP-II  
90Ball FBGA  
HY57V283220(L)T-PI  
HY5V22(L)F-PI  
4Banks x 1Mbits  
x32  
86TSOP-II  
90Ball FBGA  
HY57V283220(L)T-SI  
HY5V22(L)F-SI  
4Banks x 1Mbits  
x32  
86TSOP-II  
90Ball FBGA  
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume  
any responsibility for use of circuits described. No patent licenses are implied.  
Rev. 0.6/Nov. 02  
1234567...14

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与HY5V22LF-55I相关器件

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HY5V22LF-5I HYNIX

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 		Synchronous DRAM, 4MX32, 4.5ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90
HY5V22LF-6 HYNIX

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 		4 Banks x 1M x 32Bit Synchronous DRAM
HY5V22LF-6I HYNIX

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 		Synchronous DRAM, 4MX32, 5.5ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90
HY5V22LF-7 HYNIX

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 		4 Banks x 1M x 32Bit Synchronous DRAM
HY5V22LF-7I HYNIX

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 		Synchronous DRAM, 4MX32, 5.5ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90
HY5V22LF-8 HYNIX

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 		4 Banks x 1M x 32Bit Synchronous DRAM
HY5V22LF-8I HYNIX

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 		Synchronous DRAM, 4MX32, 6ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90
HY5V22LF-H HYNIX

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 		4 Banks x 1M x 32Bit Synchronous DRAM
HY5V22LF-P HYNIX

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 		4 Banks x 1M x 32Bit Synchronous DRAM
HY5V22LFP-5 HYNIX

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 		4 Banks x 1M x 32Bit Synchronous DRAM

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