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HY57V643220DTP-6I

更新时间： 2024-09-30 19:36:47

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HY57V643220DTP-6I 数据手册

HY57V643220D(L/S)T(P)-xI Series

4Banks x 512K x 32bits Synchronous DRAM

Document Title

4Bank x 512K x 32bits Synchronous DRAM

Revision History

Revision

History

Draft Date

Remark

No.

0.1

0.2

Initial Draft

June. 2004

July 2004

Preliminary

Removed Preliminary

1. Updated Output Load Capacitance for Access Time Measurement CL = 30pF in

AC OPERATING TEST CONDITION

2. Updated the tolerance zone of the leads and the description of the package type

in PACKAGE DIMENSION

0.3

0.4

Sep. 2004

Sep. 2005

1.Corrected : Lead range tolerance (Page : 13)

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev. 0.4 / Sep. 2005

12 3 4 5 6 7...13

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型号	品牌	获取价格	描述	数据表
HY57V643220DTP-7	HYNIX	获取价格	4Banks x 512K x 32bits Synchronous DRAM
HY57V643220DTP-7I	HYNIX	获取价格	Synchronous DRAM, 2MX32, 5.5ns, CMOS, PDSO86, 0.400 X 0.875 INCH, 0.50 MM PITCH, LEAD FREE
HY57V644010LTC-10	HYNIX	获取价格	Synchronous DRAM, 16MX4, CMOS, TSOP2
HY57V644010TC-10	ETC	获取价格	x4 SDRAM
HY57V644010TC-12	ETC	获取价格	x4 SDRAM
HY57V644010TC-15	ETC	获取价格	x4 SDRAM
HY57V644011TC-10	ETC	获取价格	x4 SDRAM
HY57V644011TC-7	ETC	获取价格	x4 SDRAM
HY57V644011TC-8	ETC	获取价格	x4 SDRAM
HY57V644020LTC-10	HYNIX	获取价格	Synchronous DRAM, 16MX4, CMOS, TSOP2