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HT82V82 PDF预览

HT82V82

更新时间: 2024-11-18 21:10:15
品牌 Logo 应用领域
台湾合泰/盛群 - HOLTEK LTE传感器换能器
页数 文件大小 规格书
26页 913K
描述
CMOS Sensor,

HT82V82 技术参数

生命周期:ActiveReach Compliance Code:unknown
风险等级:5.75传感器/换能器类型:IMAGE SENSOR,CMOS
Base Number Matches:1

HT82V82 数据手册

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HT82V82  
Image/Neural-network Processor  
Features  
Applications  
• Dual-core symmetric high-performance video DSP,  
each core contains  
• Double-sided currency detector scanner  
• License Plate Recognition System  
• Automatic Optical Inspection System  
up to 250MHz  
5-stage pipeline  
Dynamic branch prediction  
General Description  
I/D Caches, 2-way set-associative, 32KB each  
IEEE 754 Compliant single-precision Floating-  
The HT82V82 is a fully integrated device for CIS  
and CMOS image processing and deep learning  
applications. It features a state-of-the-art dual-core  
floating-point DSP core, powerful Hardware Engine  
including Video processor and NPU (Neural Processing  
Unit) to accelerate image processing and AI computing,  
programmable timing generator and video processing  
modules for high-speed double-sided scanning for  
currency detection and face recognition applications.  
-Point Unit – FPU  
Nested interrupt controller with programmable  
priority levels  
16/32-bit instruction set  
SIMD instruction set  
General DSP instructions  
Rich featured video instruction set  
• L1/L2 Memory Architecture  
The dual-core DSP processors offer performance  
up to 250MHz, each compliant with IEEE  
754 single-precision floating-point operations  
and single-instruction, multiple-data (SIMD)  
multimedia capabilities into a single instruction-set  
architecture. The hardware engine provides hardware  
implementation of signal and image processing  
algorithms like Rotation, Decimation, JPEG Encoder,  
Image Histogram, CNN, Integral Image, etc. to  
offload the dual-core DSP’s loading and accelerate  
video processing.  
32KB L1 Program Cache, each core  
16KB L1 Program RAM, each core  
32KB L1 Data Cache, each core  
32KB L1 Data RAM, each core  
256KB L2 United Mapped RAM  
• External Memory Interface  
16/32-bit DDR2/3 memory interface  
NOR Flash memory interface  
• Embedded Hardware Engine to accelerate video  
processing  
The Sensor Interface provides an interface for image  
capture from CMOS or CIS sensors. The HT82V82  
can be connected to a CMOS sensor directly through  
the sensor Interface. In conjunction with an Analog  
Front End (AFE) IC such as the HT82V48, it can also  
be connected to a CIS sensor, utilising the embedded  
Timing Generator.  
• Enhanced Direct Memory Access – EDMA  
• Sensor Input interface  
Support two 8~20MHz 3~6ch CIS line sensor  
modules  
Supports two CMOS area sensor modules  
• Output interface  
Serial interface: High speed 4-wire SPI up to  
40MHz.  
Parallel interface: TFT LCD display  
The device also includes rich peripherals for UART,  
SPI, I2C, 16-ch ADC, SDIO, EPI (external parallel  
interface) to enable simplified interfacing to existing  
control systems. A high speed synchronous memory  
interface is provided for the popular DDR2/DDR3  
memory.  
• Supports peripheral interfaces like I2C, SPI, UART,  
SPI, Timer and 16-ch 10-bit ADC  
• Supports External Parallel Interfaces – EPI  
• SDIO interface  
By providing a robust security boot mechanism, the  
HT82V82 provides users with protected proprietary  
intellectual property measures and prevents external  
entities from modifying the user-developed program code.  
Supports two different data bus modes: 1-bit  
(default) and 4-bit  
Supports two different speed modes: Normal  
speed (default) and High speed  
SD clock frequency of up to (fHCLK/2)MHz  
SPI mode and MMC stream mode not supported  
HT82V82 is the best choice for next-generation  
applications that require image processing and deep  
learning in one integrated package. These applications  
span a wide array of video markets, like high-speed  
double-sided Currency Recognition, License Plate  
Recognition, Automatic Optical Inspection and Facial  
Recognition.  
• Robust security boot mechanism  
• Embedded LVR and POR circuits  
• 256-pin TFBGA package  
Rev. 1.00  
1
November 19, 2019  

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