HT48R062/HT48C062
Cost-Effective I/O Type 8-Bit MCU
Technical Document
·
Tools Information
·
FAQs
·
Application Note
-
HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
HA0013E HT48 & HT46 LCM Interface Design
-
-
-
-
HA0016E Writing and Reading to the HT24 EEPROM with the HT48 MCU Series
HA0018E Controlling the HT1621 LCD Controller with the HT48 MCU Series
HA0049E Read and Write Control of the HT1380
Features
·
·
·
·
·
·
·
·
·
Operating voltage:
63 powerful instructions
fSYS=4MHz: 2.2V~5.5V
Up to 0.5ms instruction cycle with 8MHz system clock
All instructions in 1 or 2 machine cycles
14-bit table read instructions
fSYS=8MHz: 3.3V~5.5V
·
·
·
·
·
·
11 bidirectional I/O lines
On-chip crystal and RC oscillator
Watchdog Timer
One-level subroutine nesting
Bit manipulation instructions
1K´14 program memory
32´8 data RAM
Low voltage reset function
16-pin DIP/SOP/SSOP package
HALT function and wake-up feature reduce power
consumption
General Description
The HT48R062/HT48C062 are 8-bit high performance,
RISC architecture microcontroller devices specifically
designed for cost-effective multiple I/O control product
applications. The mask version HT48C062 is fully pin
and functionally compatible with the OTP version
HT48R062 devices.
The advantages of low power consumption, I/O flexibil-
ity, oscillator options, HALT and wake-up functions,
watchdog timer, as well as low cost, enhance the versa-
tility of these devices to suit a wide range of application
possibilities such as industrial control, consumer prod-
ucts, subsystem controllers, etc.
The HT48C062 is under development and will be avail-
able soon.
Block Diagram
S
t
a
c
k
P
r
o
g
r
a
m
P
r
o
g
r
a
m
C
o
u
n
t
e
r
M
S
y
s
t
e
m
C
l
o
c
k
/
4
I
n
s
t
r
u
c
t
i
o
n
W
D
T
U
R
e
g
i
s
t
e
r
W
D
T
O
S
C
M
M
P
¸
2
D
a
t
a
X
U
(
2
4
k
H
z
)
M
e
m
o
r
y
X
E
N
/
D
I
S
H
A
L
T
L
V
R
I
n
s
t
r
u
c
t
i
o
n
M
U
X
D
e
c
o
d
e
r
P
A
C
P
o
r
t
A
S
T
A
T
U
S
T
i
m
i
n
g
A
L
U
P
A
P
A
0
~
P
A
7
G
e
n
e
r
a
t
o
r
S
h
i
f
t
e
r
P
B
C
P
o
r
t
B
O
S
C
2
O
S
C
1
P
B
P
B
0
~
P
B
2
R
E
S
V
D
D
A
C
C
V
S
S
Rev. 1.00
1
July 13, 2006