HT45R34
by a return instruction, RET or RETI, the program counter
is restored to its previous value from the stack. After a de-
vice reset, the stack pointer will point to the top of the
stack.
I
n
d
i
r
e
c
t
A
d
d
r
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s
s
i
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g
R
e
g
i
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t
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r
0
0
0
0
1
H
H
M
P
0
I
n
d
i
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e
c
t
A
d
d
r
e
s
s
i
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R
e
g
i
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t
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r
1
0
2
H
M
P
1
0
3
H
0
4
H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is sub-
sequently executed, stack overflow occurs and the first
entry will be lost as only the most recent 4 return ad-
dresses are stored.
A
C
C
0
5
H
P
C
L
0
6
H
T
B
L
P
0
7
H
T
B
L
H
0
8
H
W
D
T
S
0
9
H
S
T
A
T
U
S
0
0
A
B
H
H
I
N
T
C
0
0
0
C
D
H
H
T
M
R
T
M
R
C
0
E
H
0
F
H
Data Memory - RAM
1
1
0
1
H
H
The data memory has a capacity of 111´8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(88´8). Most are read/write, but some are read only.
P
A
S
p
e
c
i
a
l
P
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p
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e
1
2
H
D
a
t
a
M
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m
o
r
y
P
A
C
1
3
H
1
4
H
1
5
H
The general purpose data memory, addressed from 28H
to 7FH, is used for data and control information under in-
struction commands.
1
6
H
1
7
H
1
8
H
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by the ²SET [m].i²
and ²CLR [m].i² bit manipulation instructions. They are
also indirectly accessible through the memory pointer
registers (MP0;01H, MP1;02H).
1
9
H
1
1
A
B
H
H
A
S
C
R
1
1
C
D
H
H
1
E
H
I
N
T
C
1
1
F
H
2
2
2
2
0
1
2
3
H
H
H
H
T
M
R
A
H
Indirect Addressing Register
T
M
R
A
L
R
C
O
C
C
R
The method of indirect addressing allows data manipu-
lation using memory pointers instead of the usual direct
memory addressing method where the actual memory
address is defined. Any action on the indirect address-
ing registers will result in corresponding read/write oper-
ations to the memory location specified by the
corresponding memory pointers. This device contains
two indirect addressing registers known as IAR0 and
IAR1 and two memory pointers MP0 and MP1. Note that
these indirect addressing registers are not physically
implemented and that reading the indirect addressing
registers indirectly will return a result of ²00H² and writ-
ing to the registers indirectly will result in no operation.
T
M
R
B
H
2
2
4
5
H
H
T
M
R
B
L
R
C
O
C
R
2
6
H
2
7
H
2
8
H
:
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m
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(
8
8
B
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s
)
R
e
a
d
a
s
"
0
0
"
7
F
H
RAM Mapping
Bit 7 of the memory pointers are not implemented. How-
ever, it must be noted that when the memory pointers in
this device is read, a value of ²1² will be read.
The two memory pointers, MP0 and MP1, are physically
implemented in the data memory and can be manipu-
lated in the same way as normal registers providing a
convenient way with which to address and track data.
When any operation to the relevant indirect addressing
registers is carried out, the actual address that the
microcontroller is directed to is the address specified by
the related memory pointer.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location ²05H² of the data memory
and can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
Rev. 1.20
7
October 15, 2007
5秒后页面跳转
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