3ꢅ-Bit Aꢂꢀ® Coꢂtex®-M3 MCU
HT3ꢅF1ꢅ365/HT3ꢅF1ꢅ366/HT3ꢅFꢅꢅ366
Features
2
Core
32-bit Arm® Cortex®-M3 processor core
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Up to 96 MHz operating frequency
Single-cycle multiplication and hardware division
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer
The Cortex®-M3 processor is a general-purpose 32-bit processor core especially suitable for
products requiring high performance and low power consumption microcontrollers. It offers many
special features such as a Thumb-2 instruction set, hardware divider, low latency interrupt respond
time, atomic bit-banding access and multiple buses for simultaneous accesses. The Cortex®-M3
processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction
sets.
On-chip Memory
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256 KB on-chip Flash memory for instruction/data and option storage
Up to 128 KB on-chip SRAM
Supports multiple boot modes
The Arm® Cortex®-M3 processor is structured using Harvard architecture which uses a separate
bus structure to fetch instructions and load/store data. The instruction code and data are both
located in the same memory address space but in different address ranges. The maximum address
range of the Cortex®-M3 is 4 GB due to its 32-bit bus address width. Additionally, a pre-defined
memory map is provided by the Cortex®-M3 processor to reduce the software complexity of
repeated implementation for different device vendors. However, some regions are used by the
Arm® Cortex®-M3 system peripherals. Refer to the Arm® Cortex®-M3 Technical Reference Manual
for more information. Figure 2 shows the memory map of the HT32F12365/12366/22366 series of
devices, including Code, SRAM, peripheral, and other pre-defined regions.
Flash Memory Controller – FMC
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Flash accelerator for maximum efficiency
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32-bit word programming with In System Programming Interface (ISP) and In Application
Programming (IAP)
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Flash protection capability to prevent illegal access
The Flash Memory Controller, FMC, provides all the necessary functions and pre-fetch buffer
for the embedded on-chip Flash Memory. Since the access speed of the Flash Memory is slower
than the CPU, a wide access interface with a pre-fetch buffer and cache are provided for the Flash
Memory in order to reduce the CPU waiting time which will cause CPU instruction execution
delays. Flash Memory word program/page erase functions are also provided.
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