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HSD32M72D18R-10 PDF预览

HSD32M72D18R-10

更新时间: 2022-12-21 13:43:27
品牌 Logo 应用领域
HANBIT 动态存储器
页数 文件大小 规格书
12页 177K
描述
Synchronous DRAM Module 256Mbyte (32Mx72bit), DIMM with ECC based on 16Mx8, 4Banks, 4K Ref., 3.3V

HSD32M72D18R-10 数据手册

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HANBit  
HSD32M72D18R  
Synchronous DRAM Module 256Mbyte (32Mx72bit), DIMM with ECC based on  
16Mx8, 4Banks, 4K Ref., 3.3V  
Part No. HSD32M72D18R  
GENERAL DESCRIPTION  
The HSD32M72D18R is a 32M x 72 bit Synchronous Dynamic RAM high-density memory module. The module consists  
of eighteen CMOS 16M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages and 2K EEPROM in 8-pin  
TSSOP package on a 168-pin glass-epoxy. One 0.22uF and two 0.0022uF decoupling capacitors are mounted on the  
printed circuit board in parallel for each SDRAM. The HSD32M72D18AR is a DIMM (Dual in line Memory Module) and is  
intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use  
of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable  
latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system  
applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are  
LVTTL-compatible.  
FEATURES  
Part Identification  
HSD32M72D18R : 100MHz (CL=2, CL=3)  
HSD32M72D18R : 133MHz (CL=3)  
Burst mode operation  
Auto & self refresh capability (4096 Cycles/64ms)  
LVTTL compatible inputs and outputs  
Single 3.3V ±0.3V power supply  
MRS cycle with address key programs  
- Latency (Access from column address)  
- Burst length (1, 2, 4, 8 & Full page)  
- Data scramble (Sequential & Interleave)  
All inputs are sampled at the positive going edge of the system clock  
The used device is 4M x 8bit x 4Banks SDRAM  
URL:www.hbe.co.kr  
REV.1.0 (August.2002).  
- 1 -  
HANBit Electronics Co.,Ltd  

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