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HSD16M64D16A-F10

更新时间： 2024-01-01 19:26:07

品牌	Logo	应用领域
HANBIT		动态存储器
页数	文件大小	规格书
10页	155K
描述
Synchronous DRAM Module 128Mbyte (16Mx64bit), DIMM based on 8Mx8, 4Banks, 4K Ref., 3.3V

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技术参数
数据手册

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HSD16M64D16A-F10 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.75
Is Samacsys：	N	Base Number Matches：	1

HSD16M64D16A-F10 数据手册

HANBit

HSD16M64D16A

+3.3V

V =1.4V

1200W

50pF*

50W

D_OUT

Z0=50W

870W

50pF

(DC) = 2.4V, I

= -2mA

(DC) = 0.4V, I = 2mA

(Fig. 2) AC output load circuit

(Fig. 1) DC output load

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

VERSION

PARAMETER

SYMBOL

UNIT

NOTE

-13

-12

-10

-10L

Row active to row active delay

RAS to CAS delay

t_RRD(min)

t_RP(min)

Row precharge time

t_RP(min)

t_RAS(min)

t_RAS(max)

Row active time

100

Row cycle time

_tRC(min)

t_RDL(min)

t_DAL(min)

t_CDL(min)

t_BDL(min)

t_CCD(min)

CLK

Last data in to row precharge

Last data in to Active delay

Last data in to new col. address delay

Last data in to burst stop

2 CLK + 20 ns

CLK

Col. address to col. address delay

CAS latency=3

CAS latency=2

Number of valid output data

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and

then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

.5. For -8/H/L/10, tRDL=1CLK and tDAL=1CLK+20ns is also supported .

( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.)

URL: www.hbe.co.kr

REV 1.0 (August.2002)

HANBit Electronics Co.,Ltd

1...4 5 678 9 10

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HSD16M64D16A-F10L	HANBIT	Synchronous DRAM Module 128Mbyte (16Mx64bit), DIMM based on 8Mx8, 4Banks, 4K Ref., 3.3V	获取价格
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