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HS1-303AEH-Q PDF预览

HS1-303AEH-Q

更新时间: 2024-01-02 12:25:51
品牌 Logo 应用领域
英特矽尔 - INTERSIL 开关光电二极管
页数 文件大小 规格书
5页 201K
描述
Radiation Hardened CMOS Dual SPDT Analog Switch

HS1-303AEH-Q 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.91
Is Samacsys:N模拟集成电路 - 其他类型:SPDT
JESD-30 代码:R-CDIP-T14JESD-609代码:e0
标称负供电电压 (Vsup):-15 V信道数量:1
功能数量:2端子数量:14
标称断态隔离度:40 dB最大通态电阻 (Ron):75 Ω
最高工作温度:125 °C最低工作温度:-55 °C
输出:SEPARATE OUTPUT封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:+-15 V
认证状态:Not Qualified筛选级别:MIL-PRF-38535 Class T
座面最大高度:5.08 mm子类别:Multiplexer or Switches
标称供电电压 (Vsup):15 V表面贴装:NO
最长断开时间:450 ns最长接通时间:500 ns
切换:BREAK-BEFORE-MAKE技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
总剂量:100k Rad(Si) V宽度:7.62 mm
Base Number Matches:1

HS1-303AEH-Q 数据手册

 浏览型号HS1-303AEH-Q的Datasheet PDF文件第1页浏览型号HS1-303AEH-Q的Datasheet PDF文件第2页浏览型号HS1-303AEH-Q的Datasheet PDF文件第3页浏览型号HS1-303AEH-Q的Datasheet PDF文件第4页 
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH  
Ceramic Metal Seal Flatpack Packages (Flatpack)  
K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)  
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE  
A
A
e
INCHES MILLIMETERS  
MIN  
PIN NO. 1  
ID AREA  
SYMBOL  
MAX  
0.115  
0.022  
0.019  
0.009  
0.006  
0.390  
0.260  
0.290  
-
MIN  
1.14  
0.38  
0.38  
0.10  
0.10  
-
MAX  
2.92  
0.56  
0.48  
0.23  
0.15  
9.91  
6.60  
7.11  
-
NOTES  
D
A
b
0.045  
0.015  
0.015  
0.004  
0.004  
-
-
-A-  
-B-  
S1  
-
b1  
c
-
-
b
c1  
D
E
-
E1  
3
0.004  
Q
H
A - B  
D
0.036  
H
A - B  
D
S
M
S
S
M
S
0.235  
-
5.97  
-
-
C
E
E1  
E2  
E3  
e
3
-D-  
A
0.125  
0.030  
3.18  
0.76  
-
-H-  
-C-  
-
-
7
L
E2  
L
E3  
E3  
0.050 BSC  
1.27 BSC  
-
SEATING AND  
BASE PLANE  
c1  
LEAD FINISH  
k
0.008  
0.270  
0.026  
0.005  
-
0.015  
0.370  
0.045  
-
0.20  
6.86  
0.66  
0.13  
-
0.38  
9.40  
1.14  
-
2
L
-
BASE  
METAL  
Q
S1  
M
N
8
(c)  
6
b1  
0.0015  
0.04  
-
M
M
(b)  
14  
14  
-
SECTION A-A  
Rev. 0 5/18/94  
NOTES:  
1. Index area: A notch or a pin one identification mark shall be located ad-  
jacent to pin one and shall be located within the shaded area shown.  
The manufacturer’s identification shall not be used as a pin one identi-  
fication mark. Alternately, a tab (dimension k) may be used to identify  
pin one.  
2. If a pin one identification mark is used in addition to a tab, the limits of  
dimension k do not apply.  
3. This dimension allows for off-center lid, meniscus, and glass overrun.  
4. Dimensions b1 and c1 apply to lead base metal only. Dimension M ap-  
plies to lead plating and finish thickness. The maximum limits of lead  
dimensions b and c or M shall be measured at the centroid of the fin-  
ished lead surfaces, when solder dip or tin plate lead finish is applied.  
5. N is the maximum number of terminal positions.  
6. Measure dimension S1 at all four corners.  
7. For bottom-brazed lead packages, no organic or polymeric materials  
shall be molded to the bottom of the package to cover the leads.  
8. Dimension Q shall be measured at the point of exit (beyond the menis-  
cus) of the lead from the body. Dimension Q minimum shall be reduced  
by 0.0015 inch (0.038mm) maximum when solder dip lead finish is  
applied.  
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.  
10. Controlling dimension: INCH.  
FN6411.2  
December 12, 2012  
5

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