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HS1-303AEH-Q PDF预览

HS1-303AEH-Q

更新时间: 2024-01-13 00:24:53
品牌 Logo 应用领域
英特矽尔 - INTERSIL 开关光电二极管
页数 文件大小 规格书
5页 201K
描述
Radiation Hardened CMOS Dual SPDT Analog Switch

HS1-303AEH-Q 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.91
Is Samacsys:N模拟集成电路 - 其他类型:SPDT
JESD-30 代码:R-CDIP-T14JESD-609代码:e0
标称负供电电压 (Vsup):-15 V信道数量:1
功能数量:2端子数量:14
标称断态隔离度:40 dB最大通态电阻 (Ron):75 Ω
最高工作温度:125 °C最低工作温度:-55 °C
输出:SEPARATE OUTPUT封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:+-15 V
认证状态:Not Qualified筛选级别:MIL-PRF-38535 Class T
座面最大高度:5.08 mm子类别:Multiplexer or Switches
标称供电电压 (Vsup):15 V表面贴装:NO
最长断开时间:450 ns最长接通时间:500 ns
切换:BREAK-BEFORE-MAKE技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
总剂量:100k Rad(Si) V宽度:7.62 mm
Base Number Matches:1

HS1-303AEH-Q 数据手册

 浏览型号HS1-303AEH-Q的Datasheet PDF文件第1页浏览型号HS1-303AEH-Q的Datasheet PDF文件第2页浏览型号HS1-303AEH-Q的Datasheet PDF文件第3页浏览型号HS1-303AEH-Q的Datasheet PDF文件第5页 
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH  
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)  
c1  
LEAD FINISH  
D14.3 MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)  
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE  
-A-  
-D-  
E
INCHES  
MIN  
MILLIMETERS  
BASE  
METAL  
(c)  
SYMBOL  
MAX  
0.200  
0.026  
0.023  
0.065  
0.045  
0.018  
0.015  
0.785  
0.310  
MIN  
-
MAX  
5.08  
0.66  
0.58  
1.65  
1.14  
0.46  
0.38  
19.94  
7.87  
NOTES  
b1  
A
b
-
-
M
M
(b)  
0.014  
0.014  
0.045  
0.023  
0.008  
0.008  
-
0.36  
0.36  
1.14  
0.58  
0.20  
0.20  
-
2
-B-  
b1  
b2  
b3  
c
3
SECTION A-A  
S
S
S
D
bbb  
C
A - B  
-
D
4
BASE  
S2  
Q
PLANE  
2
A
-C-  
SEATING  
PLANE  
c1  
D
3
L
-
S1  
b2  
eA  
A A  
E
0.220  
5.59  
-
e
eA/2  
aaa  
M C A - B S D S  
b
c
e
0.100 BSC  
2.54 BSC  
-
eA  
eA/2  
L
0.300 BSC  
0.150 BSC  
7.62 BSC  
3.81 BSC  
-
ccc  
M
C A - B S D S  
-
NOTES:  
0.125  
0.200  
3.18  
0.38  
0.13  
0.13  
5.08  
-
1. Index area: A notch or a pin one identification mark shall be located ad-  
jacent to pin one and shall be located within the shaded area shown.  
The manufacturer’s identification shall not be used as a pin one identi-  
fication mark.  
Q
0.015  
0.005  
0.005  
0.060  
1.52  
5
S1  
S2  
α
-
-
-
-
6
7
2. The maximum limits of lead dimensions b and c or M shall be measured  
at the centroid of the finished lead surfaces, when solder dip or tin plate  
lead finish is applied.  
o
o
o
o
90  
105  
90  
-
105  
0.38  
0.76  
0.25  
0.038  
-
aaa  
bbb  
ccc  
M
N
-
-
-
-
0.015  
0.030  
0.010  
0.0015  
-
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension M  
applies to lead plating and finish thickness.  
-
-
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial  
-
2
lead paddle. For this configuration dimension b3 replaces dimension  
b2.  
14  
14  
8
5. Dimension Q shall be measured from the seating plane to the base plane.  
6. Measure dimension S1 at all four corners.  
Rev. 0 4/94  
7. Measure dimension S2 from the top of the ceramic body to the nearest  
metallization or lead.  
8. N is the maximum number of terminal positions.  
9. Braze fillets shall be concave.  
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.  
11. Controlling dimension: INCH.  
FN6411.2  
December 12, 2012  
4

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