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HS0-302AEH-Q PDF预览

HS0-302AEH-Q

更新时间: 2024-09-23 21:21:47
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
11页 564K
描述
DPST

HS0-302AEH-Q 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:,Reach Compliance Code:compliant
风险等级:5.67模拟集成电路 - 其他类型:DPST
峰值回流温度(摄氏度):NOT SPECIFIED处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

HS0-302AEH-Q 数据手册

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DATASHEET  
Radiation Hardened CMOS Dual DPST Analog Switch  
HS-302AEH  
Features  
The HS-302AEH is a dual Double-Pole-Single Throw (DPST)  
analog switch fabricated using Intersil’s dielectrically isolated  
Radiation Hardened Silicon Gate (RSG) process technology to  
insure latch-up free operation. It is pin compatible and  
functionally equivalent to the HS-302RH.  
• Electrically screened to DLA SMD# 5962-95812  
• No latch-up, dielectrically isolated device islands  
• Pin and functionally compatible with Intersil HS-302RH  
series analog switches  
• Analog signal range equal to the supply voltage range  
This switch offers convenient switching controlled by 5V digital  
inputs and low-resistance switching performance for analog  
voltages up to the supply rails. ON-resistance is low and stays  
reasonably constant over the full range of operating voltage  
and current as well as over exposure to radiation.  
• Low leakage . . . . . . . . . . . . . . . . 150nA (maximum, post-rad)  
• Low r  
ON . . . . . . . . . . . . . . . . . . . . . . . . . .60Ω  
(maximum, post-rad)  
• Low standby supply current . . ±150µA (maximum, post-rad)  
• Radiation assurance  
The HS-302AEH is available in a 14 Ld CDFP or die form and  
operates across the extended temperature range of -55°C to  
+125°C.  
- High dose rate (50 to 300rad(Si)/s) . . . . . . . . 100krad(Si)  
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . 50krad(Si)*  
• Single event effects  
Applications  
• Signal processing applications  
• Power supply control  
2
- For LET = 60MeV•mg/cm at 60° incident angle,  
<150pC charge transferred to the output of an off switch  
* Product capability established by initial characterization. The  
EH version is acceptance tested on a wafer-by-wafer basis to  
50krad(Si) at low dose rate.  
S
60  
I
= 10mA  
= ±15V  
S
V
S
50  
40  
30  
20  
10  
0
N
P
IN  
+125°C  
D
+25°C  
-55°C  
FIGURE 1. LOGIC CIRCUIT  
TABLE 1. TRUTH TABLE  
LOGIC  
All SWITCHES  
-15  
-10  
-5  
0
5
10  
15  
VDx (V)  
0
1
OFF  
ON  
FIGURE 2. r vs SIGNAL LEVEL vs TEMPERATURE  
ON  
July 15, 2016  
FN8815.0  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2016. All Rights Reserved  
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.  
All other trademarks mentioned are the property of their respective owners.  
1

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