HRF-AT4610
31.5 dB, DC - 4GHz, 6 Bit Parallel Digital Attenuator
The Honeywell HRF-AT4610 is a 6-bit digital attenuator ideal for use in broadband
communication system applications that require accuracy, speed and low power
consumption. The HRF-AT4610 is manufactured with Honeywell's patented Silicon
On Insulator (SOI) CMOS manufacturing technology, which provides the performance
of GaAs with the economy and integration capabilities of conventional CMOS. These
attenuators are DC coupled to improve lower operating frequency, frequency
response and reduce the number of DC bias points required.
FEATURES
HRF-AT4610 in VQFN Package
Very Low DC Power Consumption
Attenuation In Steps From 0.5 dB To 31.5 dB
Single Positive Power Supply Voltage
Parallel Data Interface
50 Ohm Impedance
DC-coupled, bi-directional RF path
Space Saving VQFN Surface Mount Packaging
Lead-free, RoHS compliant and halogen-free
RF ELECTRICAL SPECIFICATIONS @ + 25oC
Results @ VDD = 5.0 +/- 10%, VSS = 0 unless otherwise stated, Z0 = 50 Ohms
Contact Honeywell for relative performance at other supply configurations
Parameter
Test Condition
Frequency
Minimum
Typical
Maximum
Units
1.0 GHz
2.5 GHz
3.0 GHz
4.0 GHz
2.5
3.0
3.6
5.5
2.9
3.5
3.9
5.8
dB
dB
dB
dB
Insertion Loss
VSS = 0V, Input Power
VSS = -3V, Input Power
2.0 GHz
2.0 GHz
24
29
dBm
dBm
1dB Compression
Input IP3
VSS = 0V
Two-tone inputs, up to +5 dBm
@ 0 dBm attenuation
dBm
2.0 GHz
2.0 GHz
38
Vss = -3V
Two-tone inputs, up to +5 dBm
@ 0 dBm attenuation
dBm
dB
Input IP3
>38
-13
Return Loss
Any Bit or Combination
-11
All attenuation states
All attenuation states
All attenuation states
All attenuation states
1.0 GHz
2.5 GHz
3.0 GHz
4.0 GHz
+/-(0.3 + 3.0% of programmed IL)
+/-(0.3 + 4.0% of programmed IL)
+/-(0.3 + 5.5% of programmed IL)
+/-(0.3 + 7.0 % of programmed IL)
dB
dB
dB
dB
Attenuation Accuracy
Trise, Tfall
Ton, Toff (Tpd)
10% To 90%
50% Cntl To 90% / 10%RF
10
15
nS
nS
T clock Period (Tprd)
T data set up (Tsup)
T data hold (Thld)
T high / T low = ½ minimum clock period
Set up to rising edge of clock
50
5
nS
nS
nS
nS
Data hold after rising edge of clock
Data set up to rising edge of OE
2
T latch set up (Tlsup)
5