Figure 3 illustrates the logic states
necessary to program both the
reference and LO2 dividers.
external tank circuit, and incorpo- The limiting amplifier chain also
rates a force (VCOA) and sense feeds the Received Signal Strength
(VCOB) architecture to reduce the Indicator (RSSI) block. The RSSI
effects of package parasitics. As
described earlier, the VCOB pin
may be overdriven by an external
LO, in which case the on-chip
sustaining amplifier acts as a
buffer stage before the
signal is monotonic over a 75 dB
dynamic range, and in its linear
range varies at 17 mV/dB. The
RSSI signal is designed to be
digitized by the CMOS burst mode
controller.
The reference divider ratios were
selected to conform to the three
most popular DECT reference
frequenciesof10.368MHz,
13.824 MHz,and18.432MHz. The
LO2 divider values allow the use
of either a 110.592 MHz or
112.32 MHz1stIFwithadivide
value of 90 (which yields a LO2 of
103.68 MHz). In addition, the
divide by 216 value permits the
use of a much higher 1st IF
(222.91 MHz,withacorrespond-
ingLO2of248.832MHz), which
enables the use of much smaller
SAW filters and relaxes the image
filtering requirements.
downconverting mixer.
The output of the limiting ampli-
fier (IFOP1) drives the discrimina-
tor circuit. This signal is fed
The buffered external output is a
differential signal (OSCOP,
OSCOPB). The buffer also
directly to one of the input ports
incorporates an AGC loop in order of a Gilbert cell mixer, and it also
to provide a sinusoidal output
signal with constant amplitude
which is insensitive to variations
in tank Q and loading. This helps
to suppress harmonics and
drives an external quadrature
network (with a recommended Q
of 8 for optimum performance).
The output of the external quadra-
ture network is then fed into the
other input port of the Gilbert cell
(via the DMOD pin). The output
of the Gilbert cell is taken at the
DMODOP pin, which drives an
external lowpass filter. To aid in
the construction of the filter, a
buffer stage is included on-chip.
The BUF1 pin is the noninverting
input of the buffer, and BUF2 is
the output, which is also con-
nected to the input of the data
slicer.
eliminates therefore the need for
an upconversion filter if the
The phase/frequency detector also HPMX-5002 is used in a system
incorporates a lock detection
feature. The user must supply a
decoupling capacitor (recom-
mended value of 1 nF) from the
together with the 2.5 GHz
upconverter/downconverter
HPMX-5001. The AGC requires an
external compensation capacitor
LKFIL pin to ground. If the loop is (recommended value 1 nF) from
not in phase lock, the LKDET pin
will sink up to 1 mA. This open
collector output is utilized so that
this signal can be wire-ORed with
the AGC pin to ground.
Signal Path
The input to the HPMX-5002 is an
other lock detection circuits, such AC-coupled IF signal (IP1). The
as from the 1LO portion of the
system. The pullup resistor can
also be tied to the CMOS positive
supply, thus eliminating potential
problems with CMOS logic high
voltages when different positive
supplies are used between the
input buffer before the
The data slicer operates on a dual
time constant architecture,
downconverting mixer requires a
decoupling capacitor from the
IPDC pin to ground (recom-
mended value 10 pF).
controlled via the TCSET pin.
During the preamble portion of a
DECT timeslot (with TCSET set to
1), the data slicer quickly acquires
the midpoint voltage of the
The buffered input is then mixed
radio and the baseband processor. with the LO2, and the output of
incoming data stream, correcting
any DC offsets that may have
When the PLL loop phase error is
lessthanapproximately0.3 radi-
ans, the LKDET current sink goes
to zero.
the mixer (IF1) drives an off-chip
bandpass filter centered at the IF2 occurred due to frequency devia-
frequency(6.9MHzfora110.592
MHz 1IF). The filtered signal is
tions within the DECT specifica-
tion. The value of this initial time
then fed to the IFIP1 pin, which is constant is determined by an
VCO Section
the input to the limiting amplifier
chain. The limiting amplifier
requires two external decoupling
capacitors from pins DC1A and
external capacitor connected
between TCNT and ground. A
10 nF capacitor allows the accu-
rate acquisition of the midpoint
voltage within half of the 16-bit
DECT preamble.
The VCO section has two major
components, a sustaining ampli-
fier and a buffered external
output. The sustaining amplifer is DC1B to ground (recommended
designed to be used with an value 10 nF).
7-112
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