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HMC699LP5ETR

更新时间: 2024-01-08 08:46:04
品牌 Logo 应用领域
亚德诺 - ADI ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
13页 1027K
描述
7 GHz Integer-N Synthesizer SMT

HMC699LP5ETR 技术参数

生命周期:Transferred包装说明:HVQCCN,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.79JESD-30 代码:S-PQCC-N32
长度:5 mm功能数量:1
端子数量:32最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE座面最大高度:1 mm
标称供电电压:5 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD宽度:5 mm
Base Number Matches:1

HMC699LP5ETR 数据手册

 浏览型号HMC699LP5ETR的Datasheet PDF文件第5页浏览型号HMC699LP5ETR的Datasheet PDF文件第6页浏览型号HMC699LP5ETR的Datasheet PDF文件第7页浏览型号HMC699LP5ETR的Datasheet PDF文件第9页浏览型号HMC699LP5ETR的Datasheet PDF文件第10页浏览型号HMC699LP5ETR的Datasheet PDF文件第11页 
HMC699LP5 / 699LP5E  
v05.0110  
7 GHz INTEGER N SYNTHESIZER  
CONTINUOUS (N = 56 - 519), NON-CONTINUOUS (N = 16 - 54)  
HMC699LP5(E) Programming  
Tꢀe decimal value of A counter and s counter can be defined aꢁ:  
N
A = int ( ) - 1  
8
and  
s = N - 8 (A + 1)  
wꢀere N = 16 to 519  
For a valid diviꢁion ratio N, tꢀe A counter and s counter muꢁt ꢁatiꢁfꢂ tꢀe condition: A +1 ≥ s  
Tꢀerefore, N = 16 to 54 will reꢁult into non-continuouꢁ diviꢁion ratio  
and N = 56 to 519 will be continuouꢁ diviꢁion ratio.  
6
Example: Given a reference frequencꢂ, Fref = 11 Mhꢃ, and VCO output frequencꢂ, Fvco = (198 to 297) Mhꢃ, reꢁultꢁ  
in N = 18 to 27. Tꢀe decimal value of A counter and s counter for N = 18 will be:  
18  
8
A = int (  
) - 1 = 1  
and  
s = 18 - 8 (1 + 1) = 2  
since tꢀe calculated value of A and s ꢁatiꢁfꢂ tꢀe condition of A + 1 ≥ s, tꢀe N = 18 iꢁ uꢁable diviꢁion ratio.  
Tꢀe diviꢁion ratio, N = 23, ꢀowever, will reꢁult in A = 1 and s = 7. Under tꢀe condition A +1 ≥ s, tꢀe diviꢁion ratio N =  
23 iꢁ not uꢁable.  
In tꢀiꢁ example, tꢀe diviꢁion ratio, N = 19 to 23 cannot be programmed and tꢀerefore, tꢀe frequencꢂ range of 209 Mhꢃ  
to 253 Mhꢃ cannot be uꢁed.  
HMC699LP5(E) Programming Truth Table, Continuous Division Ratios  
Diviꢁion  
Ratio N  
A Counter  
Decimal set  
swallow s  
Decimal set  
(LsB)  
A0  
(LsB)  
s0  
A1  
1
1
1
1
1
1
1
1
1
1
1
1
A2  
1
1
1
1
1
1
1
1
1
1
1
1
A3  
0
0
0
0
0
0
0
0
0
0
0
0
A4  
0
0
0
0
0
0
0
0
0
0
0
0
A5  
0
0
0
0
0
0
0
0
0
0
0
0
s1  
0
0
1
1
0
0
1
1
0
0
1
1
s2  
0
0
0
0
1
1
1
1
0
0
0
0
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
6
6
6
6
6
6
6
6
7
7
7
7
0
1
2
3
4
5
6
7
0
1
2
3
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
0
0
0
1
0
1
0
1
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