TM
HM-6516/883
March 1997
2K x 8 CMOS RAM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The HM-6516/883 is a CMOS 2048 x 8 Static Random
Access Memory. Extremely low power operation is achieved
by the use of complementary MOS design techniques. This
low power is further enhanced by the use of synchronous cir-
cuit techniques that keep the active (operating) power low,
which also gives fast access times. The pinout of the HM-
6516/883 is the popular 24 pin, 8-bit wide JEDEC Standard
which allows easy memory board layouts, flexible enough to
accommodate a variety of PROMs, RAMS, EPROMs, and
ROMs.
• Low Power Standby. . . . . . . . . . . . . . . . . . . 275µW Max
• Low Power Operation . . . . . . . . . . . . . .55mW/MHz Max
• Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max
• Industry Standard Pinout
• Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V VCC
• TTL Compatible
The HM-6516/883 is ideally suited for use in microprocessor
based systems. The byte wide organization simplifies the
memory array design, and keeps operating power down to a
minimum because only one device is enabled at a time. The
address latches allow very simple interfacing to recent gen-
• Static Memory Cells
• High Output Drive
eration microprocessors which employ
a multiplexed
• On-Chip Address Latches
address/data bus. The convenient output enable control also
simplifies multiplexed bus interfacing by allowing the data
outputs to be controlled independent of the chip enable.
• Easy Microprocessor Interfacing
Ordering Information
120ns
200ns
TEMPERATURE RANGE PACKAGE PKG. NO.
o
o
HM1-6516B/883
HM4-6516B/883
HM1-6516/883
-
-55 C to 125 C
CERDIP
CLCC
F24.6
J32.A
o
o
-55 C to +125 C
Pinouts
HM-6516/883
HM-6516/883
(CERDIP)
(CLCC)
TOP VIEW
TOP VIEW
PIN
NC
A0 - A10 Address Inputs
DESCRIPTION
1
No Connect
4
3
2
32 31 30
1
2
24
23
22
21
20
19
18
17
16
15
14
13
A7
A6
VCC
A8
29
28
27
26
25
24
23
22
21
A8
A6
A5
5
6
3
A9
A5
A9
E
Chip Enable/Power Down
4
W
A4
NC
A4
A3
7
8
5
A3
G
VSS/GND Ground
DQ0 - DQ7 Data In/Data Out
W
G
6
A10
E
A2
9
A2
7
A1
A1
A10
E
10
11
12
13
VCC
W
Power (+5V)
Write Enable
Output Enable
8
A0
DQ7
DQ6
DQ5
DQ4
DQ3
A0
9
DQ0
DQ1
DQ2
GND
10
11
12
NC
DQ0
DQ7
DQ6
G
14
15 16 17 18 19 20
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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FN2999.1
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