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HM1-6514S/883 PDF预览

HM1-6514S/883

更新时间: 2024-02-17 04:32:22
品牌 Logo 应用领域
英特矽尔 - INTERSIL 内存集成电路静态存储器输出元件输入元件双倍数据速率
页数 文件大小 规格书
9页 186K
描述
1024 x 4 CMOS RAM

HM1-6514S/883 技术参数

生命周期:Contact Manufacturer包装说明:DIP,
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.32.00.41风险等级:5.77
最长访问时间:120 ns其他特性:ADDRESS LATCH; LOW POWER STANDBY MODE; TTL COMPATIBLE INPUTS/OUTPUTS
JESD-30 代码:R-GDIP-T18内存密度:4096 bit
内存集成电路类型:STANDARD SRAM内存宽度:4
功能数量:1端子数量:18
字数:1024 words字数代码:1000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:1KX4
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子位置:DUALBase Number Matches:1

HM1-6514S/883 数据手册

 浏览型号HM1-6514S/883的Datasheet PDF文件第2页浏览型号HM1-6514S/883的Datasheet PDF文件第3页浏览型号HM1-6514S/883的Datasheet PDF文件第4页浏览型号HM1-6514S/883的Datasheet PDF文件第5页浏览型号HM1-6514S/883的Datasheet PDF文件第6页浏览型号HM1-6514S/883的Datasheet PDF文件第7页 
TM  
HM-6514/883  
March 1997  
1024 x 4 CMOS RAM  
Features  
Description  
• This Circuit is Processed in Accordance to MIL-STD-  
883 and is Fully Conformant Under the Provisions of  
Paragraph 1.2.1.  
The HM-6514/883 is a 1024 x 4 static CMOS RAM fabri-  
cated using self-aligned silicon gate technology. The device  
utilizes synchronous circuitry to achieve high performance  
and low power operation.  
• Low Power Standby. . . . . . . . . . . . . . . . . . . 125µW Max  
• Low Power Operation . . . . . . . . . . . . . .35mW/MHz Max  
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min  
• TTL Compatible Input/Output  
On chip latches are provided for addresses allowing efficient  
interfacing with microprocessor systems. The data output  
can be forced to a high impedance state for use in expanded  
memory arrays.  
• Common Data Input/Output  
Gated inputs allow lower operating current and also eliminates  
the need for pull up or pull down resistors. The HM-6514/883 is  
fully static RAM and may be maintained in any state for an  
indefinite period of time.  
• Three-State Output  
• Standard JEDEC Pinout  
• Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max  
• 18 Pin Package for High Density  
Data retention supply voltage and supply current are guaran-  
teed over temperature.  
• Gated Inputs - No Pull Up or Pull Down Resistors  
Required  
• On-Chip Address Register  
Ordering Information  
120ns  
200ns  
300ns  
TEMPERATURE RANGE  
PACKAGE  
PKG. NO.  
o
o
HM1-6514S/883  
HM1-6514B/883  
HM1-6514/883  
-55 C to 125 C  
CERDIP  
F18.3  
Pinout  
HM-6514/883  
(CERDIP)  
TOP VIEW  
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
10  
A6  
A5  
VCC  
A7  
A4  
A8  
A3  
A9  
A0  
DQ0  
DQ1  
DQ2  
DQ3  
W
A1  
A2  
E
GND  
PIN  
DESCRIPTION  
Address Input  
Chip Enable  
Write Enable  
Data Input  
A
E
W
D
Q
Data Output  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.  
FN2996.1  
Copyright © Intersil Americas Inc. 2002. All Rights Reserved  
151  

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