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HI1-574ALD-5

更新时间： 2024-01-10 02:44:07
品牌 Logo 应用领域
英特矽尔 - INTERSIL 转换器微处理器
页数 文件大小 规格书
18页 202K
描述
Complete, 12-Bit A/D Converters with Microprocessor Interface

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中文翻译

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HI1-574ALD-5 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：DIP, DIP28,.6Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.7最大模拟输入电压：24 V
最小模拟输入电压：-24 V最长转换时间：25 µs
转换器类型：ADC, SUCCESSIVE APPROXIMATIONJESD-30 代码：R-CDIP-T28
JESD-609代码：e0最大线性误差 (EL)：0.012%
位数：12功能数量：1
端子数量：28最高工作温度：75 °C
最低工作温度：输出位码：BINARY, OFFSET BINARY
输出格式：PARALLEL, WORD封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DIP封装等效代码：DIP28,.6
封装形状：RECTANGULAR封装形式：IN-LINE
电源：5,+-12/+-15 V认证状态：Not Qualified
采样速率：0.05 MHz子类别：Analog to Digital Converters
表面贴装：NO技术：BIPOLAR
温度等级：COMMERCIAL EXTENDED端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUALBase Number Matches：1

HI1-574ALD-5 数据手册

 浏览型号HI1-574ALD-5的Datasheet PDF文件第7页浏览型号HI1-574ALD-5的Datasheet PDF文件第8页浏览型号HI1-574ALD-5的Datasheet PDF文件第9页浏览型号HI1-574ALD-5的Datasheet PDF文件第11页浏览型号HI1-574ALD-5的Datasheet PDF文件第12页浏览型号HI1-574ALD-5的Datasheet PDF文件第13页 
HI-574A, HI-674A, HI-774  
Definitions of Specifications  
Pin Descriptions  
Linearity Error  
PIN  
1
SYMBOL  
DESCRIPTION  
Logic supply pin (+5V)  
Linearity error refers to the deviation of each individual code  
from a line drawn from “zero” through “full scale”. The point  
used as “zero” occurs / LSB (1.22mV for 10V span) before  
2
the first code transition (all zeros to only the LSB “on”). “Full  
V
LOGIC  
1
2
12/8  
Data Mode Select - Selects between  
12-bit and 8-bit output modes.  
1
scale” is defined as a level 1 / LSB beyond the last code tran-  
2
sition (to all ones). The deviation of a code from the true straight  
line is measured from the middle of each particular code.  
3
4
5
6
CS  
Chip Select - Chip Select high disables  
the device.  
The HI-X74(A)K and L grades are guaranteed for maximum  
1
A
Byte Address/Short Cycle - See Table  
1 for operation.  
O
nonlinearity of ± / LSB. For these grades, this means that an  
2
analog value which falls exactly in the center of a given code  
width will result in the correct digital output code. Values nearer  
the upper or lower transition of the code width may produce the  
next upper or lower digital output code. The HI-X74(A)J is  
guaranteed to ±1 LSB max error. For this grade, an analog  
value which falls within a given code width will result in either  
the correct code for that region or either adjacent one.  
R/C  
CE  
Read/Convert - See Table 1 for  
operation.  
Chip Enable - Chip Enable low disables  
the device.  
7
8
V
Positive Supply (+12V/+15V)  
+10V Reference  
CC  
Note that the linearity error is not user-adjustable.  
REF OUT  
AC  
Differential Linearity Error (No Missing Codes)  
A specification which guarantees no missing codes requires  
that every code combination appear in a monotonic increas-  
ing sequence as the analog input level is increased. Thus  
every code must have a finite width. For the HI-X74(A)K and L  
grades, which guarantee no missing codes to 12-bit resolu-  
tion, all 4096 codes must be present over the entire operating  
temperature ranges. The HI-X74(A)J grade guarantees no  
missing codes to 11-bit resolution over temperature; this  
means that all code combinations of the upper 11 bits must be  
present; in practice very few of the 12-bit codes are missing.  
9
Analog Common  
10  
11  
12  
13  
REF IN  
Reference Input  
V
Negative Supply (-12V/-15V).  
Bipolar Offset  
EE  
BIP OFF  
10V Input  
10V Input - Used for 0V to 10V and -5V  
to +5V input ranges.  
14  
20V Input  
20V Input - Used for 0V to 20V and -10V  
to +10V input ranges.  
Unipolar Offset  
1
The first transition should occur at a level / LSB above analog  
2
common. Unipolar offset is defined as the deviation of the  
actual transition from that point. This offset can be adjusted as  
discussed on the following pages. The unipolar offset tempera-  
ture coefficient specifies the maximum change of the transition  
point over temperature, with or without external adjustment.  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
DC  
DB0  
DB1  
DB2  
DB3  
DB4  
DB5  
DB6  
DB7  
DB8  
DB9  
DB10  
DB11  
STS  
Digital Common  
Data Bit 0 (LSB)  
Data Bit 1  
Bipolar Offset  
Data Bit 2  
Similarly, in the bipolar mode, the major carry transition  
Data Bit 3  
(0111 1111 1111 to 1000 0000 0000) should occur for an  
1
analog value  
/ LSB below analog common. The bipolar  
2
Data Bit 4  
offset error and temperature coefficient specify the initial  
deviation and maximum change in the error over tempera-  
ture.  
Data Bit 5  
Data Bit 6  
Full Scale Calibration Error  
Data Bit 7  
The last transition (from 1111 1111 1110 to 1111 1111  
1
1111) should occur for an analog value 1 / LSB below the  
2
Data Bit 8  
nominal full scale (9.9963V for 10.000V full scale). The full  
scale calibration error is the deviation of the actual level at  
the last transition from the ideal level. This error, which is  
typically 0.05 to 0.1% of full scale, can be trimmed out as  
shown in Figures 2 and 3. The full scale calibration error  
over temperature is given with and without the initial error  
trimmed out. The temperature coefficients for each grade  
indicate the maximum change in the full scale gain from the  
initial value using the internal 10V reference.  
Data Bit 9  
Data Bit 10  
Data Bit 11 (MSB)  
Status Bit - Status high implies a  
conversion is in progress.  
6-961  
1...78910111213...18

中文翻译

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