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HI-6121PQTF

更新时间： 2024-09-30 05:36:07

品牌	Logo	应用领域
HOLTIC		微控制器和处理器串行IO控制器通信控制器外围集成电路数据传输时钟
页数	文件大小	规格书
116页	470K
描述
MIL-STD-1553 Remote Terminal ICs

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HI-6121PQTF 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	LQFP,	针数：	52
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.65
Is Samacsys：	N	地址总线宽度：
边界扫描：	NO	最大时钟频率：	50 MHz
通信协议：	MIL STD 1553B	数据编码/解码方法：	BIPH-LEVEL(MANCHESTER)
最大数据传输速率：	0.125 MBps	外部数据总线宽度：
JESD-30 代码：	S-PQFP-G52	JESD-609代码：	e3
长度：	10 mm	低功率模式：	NO
湿度敏感等级：	3	串行 I/O 数：	2
端子数量：	52	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压：	3.45 V	最小供电电压：	3.15 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	10 mm
uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553	Base Number Matches：	1

HI-6121PQTF 数据手册

HI-6120 Parallel Bus Interface and

HI-6121 Serial Peripheral Interface (SPI)

MIL-STD-1553 Remote Terminal ICs

November 2009

GENERALDESCRIPTION

REMOTE TERMINALFEATURES

The HI-6120 and HI-6121 provide a complete, integrated,

3.3V MIL-STD-1553 Remote Terminal in a monolithic

silicon gate CMOS device. Two host interface options are

offered: The HI-6120 uses a 16-bit parallel host bus

interface for access to registers and RAM and is offered in

a 100-pin plastic quad flat pack (PQFP). The HI-6121 has a

4-wire SPI (Serial Peripheral Interface) host connection

and comes in a reduced pin count 52-pin PQFP or 64-pin

QFN. Both devices handle all aspects of the MIL-STD-

1553 protocol, including message encoding, decoding,

error detection, illegal command detection and data

buffering. Host data management is simplified by storing

message information and data within the on-chip 32K x 16

static RAM.

Fully integrated 3.3V Remote Terminal meets all

requirements for MIL-STD-1553B Notice 2

Four data buffer methods for subaddress transmit and

receive commands: indexed (single) buffering, ping-

pong (double) buffering and two circular buffer modes

Independently selectable data buffer modes for

transmit and receive commands on each subaddress

Simplified mode code command handling

Integral 16-bit Time-Tag counter has programmable

options for clock, interrupts and auto-synchronization

Message information and time-tag words are stored

with message data words for all transacted messages

A descriptor table in shared RAM provides fully

programmable memory management. Multiple descriptor

tables can be implemented for fast context switching.

Transmit and receive commands can use any of four

different data buffer modes: indexed (single) buffering,

ping-pong (double) buffering or two circular buffer

schemes. Transmit and receive commands for each

subaddress may use different buffer modes. Mode code

commands employ a simple scheme for storing mode data

and message information with programmable interrupts.

In compliance with MIL-STD-1553B Notice 2, received

data from broadcast messages may be optionally

separated from non-broadcast received data

Optional interrupt log buffer stores the most recent 16

interrupts to minimize host service duties

Optional illegal command detection uses internal table

Optional automatic self-initialization at reset

+/- 8kV ESD Protection (HBM, all pins)

MIL-STD-1760 compliant

The device provides internal illegalization capability,

allowing any subset of subaddress, command T/R bit,

broadcast vs non-broadcast and word count (or mode

code) to be illegalized, resulting in a total of 4,096 possible

combinations. The illegalization table resides in internal

RAM. The RT can also operate without illegal command

detection, providing “in form” responses to all valid

commands. Broadcast command recognition is optional.

PIN CONFIGURATION (Top View)

HI-6121 in 52-PQFP Package

The HI-6120 and HI-6121 provide programmable

interrupts for automatic message handling, message

status and general status. A host interrupt history log

maintains information about the last 16 interrupts.

COMP -

CE -

MODE -

SI -

SCK -

SO -

MCLK -

RTA0 -

RTA1 -

RTA2 - 10

MR - 11

RTA3 - 12

RTA4 - 13

39 - TEST

38 - LOCK

37 - MTSTOFF

36 - BUSA

35 - VCCP

34 - BUSA

33 - BUSB

32 - VCCP

31 - BUSB

30 - TEST0

29 - TEST1

28 - TEST2

27 - TEST3

HI-6121PQx

The HI-6120 and HI-6121 can be configured for automatic

self-initialization. A dedicated SPI port reads data from

external serial EEPROM memory to fully configure the

descriptor table, illegalization table and host interrupts.

Internal dual-redundant transceivers provide direct

connection to bus isolation transformers. The device is

offered with industrial temperature range. Extended

temperature range is also offered, with optional burn-in. A

“RoHS compliant” lead-free option is offered.

HOLT INTEGRATED CIRCUITS

www.holtic.com

HI-6120 Rev New

11/09

12 3 4 5 6 7...116

中文翻译

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与HI-6121PQTF相关器件

型号	品牌	获取价格	描述	数据表
HI-6130	HOLTIC	获取价格	3.3V BC / MT / RT Multi-Terminal Device
HI-6131	HOLTIC	获取价格	3.3V BC / MT / RT Multi-Terminal Device
HI-6132	HOLTIC	获取价格	3.3V BC / MT / RT Multi-Terminal Device
HI-6140	HOLTIC	获取价格	10 MBit/s MIL-STD-1553 3.3V BC / MT / RT
HI63SC	ETC	获取价格	TRIAC\|600V V(DRM)\|3A I(T)RMS\|TO-5
HI63SD	HUTSON	获取价格	4 Quadrant Logic Level TRIAC, 600V V(DRM), 3A I(T)RMS, TO-5,
HI63SG	HUTSON	获取价格	4 Quadrant Logic Level TRIAC, 600V V(DRM), 3A I(T)RMS, TO-5,
HI63SH	HUTSON	获取价格	4 Quadrant Logic Level TRIAC, 600V V(DRM), 3A I(T)RMS, TO-5,
HI63SS	HUTSON	获取价格	暂无描述
HI649A	HSMC	获取价格	PNP EPITAXIAL PLANAR TRANSISTOR

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