HI-6130 / HI-6131 / HI-6132
MIL-STD-1553 / MIL-STD-1760
3.3V BC / MT / RT Multi-Terminal Device
December, 2012
•
Fully programmable Bus Controller with 28 op
code instruction set.
GENERAL DESCPIPTION
The 3.3V CMOS HI-613x device provides a complete
single- or multi-function interface between a host
processor and MIL-STD-1553B bus. Each IC contains
a Bus Controller (BC), a Bus Monitor Terminal (MT)
and two independent Remote Terminals (RTs). Any
combination of the contained 1553 functions can
be enabled for concurrent operation. The enabled
terminals communicate with the MIL-STD-1553 buses
through a shared on-chip dual bus transceiver and
external transformer. The user allocates 64K bytes of
on-chip static RAM between devices to suit application
requirements.
•
Simple Monitor Terminal (SMT) Mode records
commands and data separately, with 16-bit or 48-
bit time tagging.
•
•
IRIG Monitor Terminal (IMT) Mode supports IRIG-
106 Chapter 10 packet format.
IMT Monitor Mode can optionally generate
complete IRIG-106 data packets, including full
packet headers and trailers.
•
•
Independent 16-bit time tag counters and clock
sources for all terminals. The Bus Controller
and Monitor also have 32- and 48-bit time count
options, respectively.
Two options are offered for host access to internal
registers and static RAM: The HI-6130 uses a 16-bit
parallel bus; the HI-6131 communicates with the host
via a 4-wire serial peripheral interface (SPI). The HI-
6132 combines both 16-bit parallel bus and SPI in a
single 15 x 15mm hermetically sealed ceramic package.
64-Word Interrupt Log Buffer queues the most
recent 32 interrupts. Hardware-assisted interrupt
decoding quickly identifies interrupt sources.
•
•
Built-in self-test for protocol logic, digital signal
paths and internal RAM.
Optional self-initialization at reset uses external
serial EEPROM.
Device
Host Interface Packages
•
•
±8kV ESD Protection (HBM, all pins).
HI-6130
HI-6131
16-bit parallel 100-pin PQFP
Two temperature ranges: -40oC to +85oC, or
4-wire SPI
64-pin QFN
-55oC to +125oC with optional burn-in.
64-pin PQFP
•
RoHS compliant.
HI-6132
16-bit parallel 121 ceramic PGA
or 4-wire SPI or LGA
PIN CONFIGURATION (TOP)
Programmable interrupts provide terminal status
to the host processor. Circular data buffers in RAM
have interrupts for rollover and programmable “level
attained”. The HI-613x can be configured for automatic
self-initialization after reset. A dedicated SPI port reads
data from an external serial EEPROM to fully configure
registers and RAM for any subset of one to four terminal
devices.
75 - D1
74 - D0
VCC - 1
GND - 2
BCTRIG - 3
D12 - 4
D13 - 5
D14 - 6
D15 - 7
RAMEDC - 8
CE - 9
MODE - 10
STR / OE - 11
73 - WPOL
72 - BTYPE
71 - BENDI
70 - TEST
69 - RT1LOCK
68 - MTSTOFF
67 - BCENA
66 - BUSA
65 - VCCP
64 - BUSA
63 - BUSB
62 - VCCP
61 - BUSB
60 - RT2ENA
59 - RT2A_0
58 - RT2A_1
57 - RT2A_2
56 - RT2A_3
55 - BWID
54 - A15
VCC - 12
MCLK - 13
HI-6130PQxF
FEATURES
GND - 14
WAIT / WAIT - 15
R/W / WE - 16
RT1A_0 - 17
RT1A_1 - 18
RT1A_2 - 19
MR - 20
•
Concurrent multi-terminal operation for one to
four MIL-STD-1553B functions: BC, MT and two
independent RTs.
RT1A_3 - 21
RT1A_4 - 22
A0 - 23
53 - A14
52 - A12
51 - A13
•
•
•
64K bytes internal static RAM with RAM Error
Detection/Correction option.
A1 - 24
A2 - 25
TOP VIEW
Autonomous terminal operation requires minimal
host intervention.
Shared MIL-STD-1553 bus interface reduces
circuit complexity and circuit board area.
HOLT INTEGRATED CIRCUITS
www.holtic.com
1
DS6130 Rev. F
12/12
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