Datasheet > 驱动程序和接口 > 线路驱动器或接收器> HI-3584ACJIF

HI-3584ACJIF

更新时间： 2024-02-09 17:36:08

品牌	Logo	应用领域
HOLTIC		/
页数	文件大小	规格书
16页	121K
描述
ARINC 429 3.3V Serial Transmitter

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技术参数
数据手册

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HI-3584ACJIF 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	QFP	包装说明：	QFP,
针数：	52	Reach Compliance Code：	unknown
HTS代码：	8542.31.00.01	风险等级：	5.23
Is Samacsys：	N	边界扫描：	NO
最大时钟频率：	1 MHz	最大数据传输速率：	0.0152587890625 MBps
外部数据总线宽度：	16	JESD-30 代码：	S-PQFP-G52
JESD-609代码：	e3	长度：	10 mm
低功率模式：	NO	串行 I/O 数：	1
端子数量：	52	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装形状：	SQUARE
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	2.44 mm
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	10 mm
uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	Base Number Matches：	1

HI-3584ACJIF 数据手册

HI-3584A

FUNCTIONAL DESCRIPTION (cont.)

Once a valid ARINC word is loaded into the FIFO, then EOS

clocks the data ready flag flip flop to a "1", D/R1 or D/R2 (or both)

will go low. The data flag for a receiver will remain low until both

ARINC bytes from that receiver are retrieved and the FIFO is

empty. This is accomplished by first activating EN with SEL, the

byte selector, low to retrieve the first byte and then activating EN

with SEL high to retrieve the second byte. EN1 retrieves data

from receiver 1 and EN2 retrieves data from receiver 2.

READING LABELS

After the write that changes CR1 from 0 to 1, the next 16 data

reads of the selected receiver (EN taken low) are labels. EN1 is

used to read labels for receiver 1, and EN2 to read labels for

receiver 2. Label data is presented on BD00 - BD07.

When writing to, or reading from the label memory, SEL must be a

one, all 16 locations should be accessed, and CR1 must be

written to zero before returning to normal operation. Label

recognition must be disabled (CR2/3=0) during the label read

sequence.

Up to 32 ARINC words may be loaded into each receiver’s FIFO.

The FF1 (FF2) pin will go low when the receiver 1 (2) FIFO is full.

Failure to retrieve data from a full FIFO will cause the next valid

ARINC word received to overwrite the existing data in FIFO

location 32. A FIFO half full flag HF1 (HF2) goes low if the FIFO

contains 16 or more receivedARINC words. The HF1 (HF2) pin is

intended to act as an interrupt flag to the system’s external

microprocessor, allowing a 16 word data retrieval routine to be

performed, without the user needing to continually poll the HI-

3584A’s status register bits.

TRANSMITTER

FIFO OPERATION

The FIFO is loaded sequentially by first pulsing PL1 to load byte 1

and then PL2 to load byte 2. The control logic automatically loads

the 31 bit word (or 32 bit word if CR4=0) in the next available

position of the FIFO. If TX/R, the transmitter ready flag is high

(FIFO empty), then up to 32 words, each 31 or 32 bits long, may

be loaded. If TX/R is low, then only the available positions may be

loaded. If all 32 positions are full, the FFT flag is asserted and the

FIFO ignores further attempts to load data.

LABEL RECOGNITION

The chip compares the incoming label to the stored labels if label

recognition is enabled. If a match is found, the data is processed.

If a match is not found, no indicators of receiving ARINC data are

presented. Note that 00(Hex) is treated in the same way as any

other label value. Label bit significance is not changed by the

status of control register bit CR15. Label bits BD00-BD07 are

always compared to receivedARINC bits 1 -8 respectively.

A transmitter FIFO half-full flag HFT is provided. When the

transmit FIFO contains less than 16 words, HFT is high,

indicating to the system microprocessor that a 16 ARINC word

block write sequence can be initiated.

LOADING LABELS

In normal operation (CR4=1), the 32nd bit transmitted is a parity

bit. Odd or even parity is selected by programming control

then all 32-bits of data loaded into the transmitter FIFO are

treated as data and are transmitted.

After a write that takes CR1 from 0 to 1, the next 16 writes of data

(PL pulsed low) load label data into each location of the label

memory from the BD00 - BD07 pins. The PL1 pin is used to write

label data for receiver 1 and PL2 for receiver 2. Note that ARINC

word reception is suspended during the label memory write

sequence.

CR4,12

PARITY

DATA AND

429DO

NULL TIMER

SEQUENCER

BIT CLOCK

32 BIT PARALLEL

LOAD SHIFT REGISTER

GENERATOR

429DO

BIT

AND

WORD GAP

COUNTER

WORD CLOCK

START

SEQUENCE

ADDRESS

32 x 32 FIFO

TX/R

HFT

WORD COUNTER

AND

FIFO CONTROL

FFT

LOAD

ENTX

INCREMENT

WORD COUNT

FIFO

SEQUENCER

PL1

PL2

DATA BUS

DATA

CLOCK

CLK

DATA CLOCK

DIVIDER

TX CLK

CR13

FIGURE 3. TRANSMITTER BLOCK DIAGRAM

HOLT INTEGRATED CIRCUITS

1...3 4 567 8 9...16

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