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HFIXF1110CCB2 PDF预览

HFIXF1110CCB2

更新时间: 2024-01-07 21:14:24
品牌 Logo 应用领域
英特尔 - INTEL 时钟局域网数据传输外围集成电路
页数 文件大小 规格书
183页 2578K
描述
LAN Controller, 10 Channel(s), 125MBps, CMOS, CBGA552, 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-552

HFIXF1110CCB2 技术参数

生命周期:Transferred零件包装代码:BGA
包装说明:BGA,针数:552
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.73其他特性:ALSO REQUIRES 2.5V SUPPLY
地址总线宽度:11边界扫描:YES
最大时钟频率:125 MHz最大数据传输速率:125 MBps
外部数据总线宽度:32JESD-30 代码:S-CBGA-B552
长度:25 mm低功率模式:YES
串行 I/O 数:10端子数量:552
最高工作温度:70 °C最低工作温度:
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:BGA
封装形状:SQUARE封装形式:GRID ARRAY
认证状态:Not Qualified座面最大高度:4.237 mm
最大供电电压:1.89 V最小供电电压:1.71 V
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM宽度:25 mm
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LANBase Number Matches:1

HFIXF1110CCB2 数据手册

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Intel® IXF1110 10-Port 1000 Mbps  
Ethernet Media Access Controller  
Datasheet  
The Intel® IXF1110 MAC is a 10-port Ethernet Media Access Controller (MAC) that supports  
IEEE 802.3 1000 Mbps applications. The device supports a System Packet Interface Level 4  
Phase 2 (SPI4-2) system interface to the network processor or ASIC.  
The IXF1110 MAC implements an internal Serializer/Deserializer (SerDes) to allow direct  
connection to optical modules. The integration of the SerDes functionality reduces PCB real-  
estate and system-cost requirements.  
Applications  
In general, the Intel® IXF11101000 Mbps Ethernet Media Access Controller (called hereafter  
the IXF1110 MAC) is appropriate for high-end switching applications where MAC and SerDes  
functions are not integrated into the system ASIC.  
High-End Optical Ethernet Switches  
Multi-Service Optical Ethernet Switches  
High-End Ethernet LAN/WAN Routers  
Product Features  
SerDes interface with optical module  
connections for Ethernet physical connectivity  
Integrated termination  
Supports IEEE 802.3 fiber auto-negotiation,  
including forced mode  
SFP MSA compatible  
I2C Read/Write capability  
Internal 17.0 KB receive FIFO and 4.5 KB  
transmit FIFO per port  
System Packet Interface Level 4 Phase 2 (SPI4-  
2)  
Independent enable/disable of any port  
Capable of data transfers from 10.24 Gbps up to Detection of overly large packets  
12.8 Gbps  
Supports dynamic phase alignment  
Integrated termination  
Counters for dropped and errored packets  
CRC calculation and error detection  
Programmable options:  
Ten independent 1000 Mbps full-duplex  
Ethernet MAC ports  
32-bit CPU interface  
Operating Temperature Range:  
— Min: 0 °C Max: +70 °C  
RMON statistics  
— Filter packets with errors  
— Filter, broadcast, multicast, and unicast  
address packets  
— Automatically pad transmitted packets less  
than the minimum frame size  
552-Ceramic BGA  
552-Ceramic BGA (RoHS-compliant)  
1.8 V and 2.5 V operation  
JTAG boundary scan  
Compliant with IEEE 802.3x Standard for flow  
control  
Power consumption: 490 mW per-port typical  
Jumbo frame support for 9.6 KB packets  
.18 μ CMOS process technology  
Order Number: 250210, Revision: 009  
07-Oct-2005  

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