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HEF40193BPN PDF预览

HEF40193BPN

更新时间: 2024-11-18 20:24:03
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
18页 142K
描述
IC 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP16, PLASTIC, SOT-38-1, DIP-16, Counter

HEF40193BPN 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否Rohs认证:符合
生命周期:Obsolete零件包装代码:DIP
包装说明:PLASTIC, SOT-38-1, DIP-16针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.26Is Samacsys:N
其他特性:TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK计数方向:BIDIRECTIONAL
系列:4000/14000/40000JESD-30 代码:R-PDIP-T16
长度:21.6 mm负载/预设输入:YES
逻辑集成电路类型:BINARY COUNTER工作模式:SYNCHRONOUS
位数:4功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):245
传播延迟(tpd):425 ns认证状态:Not Qualified
座面最大高度:4.7 mm最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:18 MHz
Base Number Matches:1

HEF40193BPN 数据手册

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HEF40193B  
4-bit up/down binary counter  
Rev. 06 — 22 December 2009  
Product data sheet  
1. General description  
The HEF40193B is a 4-bit synchronous up/down binary counter. The counter has a  
count-up clock input (CPU), a count-down clock input (CPD), an asynchronous parallel  
load input (PL), four parallel data inputs (D0 to D3), an asynchronous master reset input  
(MR), four counter outputs (Q0 to Q3), an active LOW terminal count-up (carry) output  
(TCU), and an active LOW terminal count-down (borrow) output (TCD).  
The counter outputs change state on the LOW-to-HIGH transition of either clock input.  
However, for correct counting, both clock inputs cannot be LOW simultaneously. The  
outputs TCU and TCD are normally HIGH. When the circuit has reached the maximum  
count state of ‘15’, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW.  
TCU will stay LOW until CPU goes HIGH again. Likewise, output TCD will go LOW when  
the circuit is in the zero state and CPD goes LOW. When PL is LOW, the information on  
D0 to D3 is asynchronously loaded into the counter. A HIGH on MR resets the counter  
independent of all other input conditions. The counter stages are of a static toggle type  
flip-flop.  
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS  
(usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is  
also suitable for use over the industrial (40 °C to +85 °C) temperature range.  
2. Features  
„ Fully static operation  
„ 5 V, 10 V, and 15 V parametric ratings  
„ Standardized symmetrical output characteristics  
„ Operates across the automotive temperature range 40 °C to +85 °C  
„ Complies with JEDEC standard JESD 13-B  
3. Applications  
„ Industrial  
 
 
 

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