Datasheet > HDD32M72D9RPW

HDD32M72D9RPW

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
HANBIT		动态存储器双倍数据速率
页数	文件大小	规格书
10页	407K
描述
DDR SDRAM Module 256Mbyte (32Mx72bit), based on 32Mx8, 4Banks 8K Ref., 184Pin-DIMM with PLL & Register

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HDD32M72D9RPW 数据手册

HANBit

HDD32M72D9RPW

ABSOLUTE MAXIMUM RATINGS

PARAMETER

Voltage on any pin relative to Vss

Voltage on V_DDsupply relative to Vss

Voltage on V_DDQsupply relative to Vss

Storage temperature

SYMBOL

V_IN, V_OUT

V_DD

RATING

UNTE

-0.5 ~ 3.6

-1.0 ~ 3.6

-55 ~ +150

13.5

V_DDQ

T_STG

°C

Power dissipation

P_D

Short circuit current

I_OS

Notes: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

POWER & DC OPERATING CONDITIONS

(Recommended operating conditions (Voltage referenced to Vss = 0V, T_A= 0 to 70°C) )

PARAMETER

SYMBOL

V_DD

MIN

2.3

MAX

2.7

UNIT

NOTE

Supply Voltage

I/O Supply Voltage

V_DDQ

2.3

2.7

I/O Reference Voltage

V_REF

V_DDQ/2-50mV

V_REF– 0.04

V_REF+ 0.15

-0.3

V_DDQ/2+50mV

V_REF+ 0.04

V_REF+ 0.3

V_REF- 0.15

V_DDQ+ 0.3

V_DDQ+ 0.6

I/O Termination Voltage(system)

Input High Voltage

V_TT

V_IH(DC)

V_IL(DC)

V_IN(DC)

V_ID(DC)

I _LI

Input Low Voltage

Input Voltage Level, CK and /CK inputs

Input Differential Voltage, CK and /CK inputs

Input leakage current

-0.3

0.3

-2

Output leakage current

I _OZ

-5

Output High current (Normal strengh driver)

;V_OUT= V_TT+ 0.84V

I _OH

I _OL

I_OH

I_OL

-16.8

16.8

-9

Output Low current (Normal strengh driver)

;V_OUT= V_TT- 0.84V

Output High current (Half strengh driver)

;V_OUT= V_TT+ 0.45V

Output Low current (Half strengh driver)

;V_OUT= V_TT- 0.45V

Notes

1. Includes ± 25mV margin for DC offset on V_REF, and a combined total of ± 50mV margin for all AC noise and DC offset on V_REF

bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V_REFand internal DRAM noise coupled

TO V_REF, both of which may result in V_REFnoise. V_REFshould be de-coupled with an inductance of £ 3nH.

2. V_TTis not applied directly to the device. V _TTis a system supply for signal termination resistors, is expected to be set equal to

V_REF, and must track variations in the DC level of V_REF

3. V_IDis the magnitude of the difference between the input level on CK and the input level on CK.

4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in

simulation. The AC and DC input specifications are relative to a V_REFenvelop that has been bandwidth limited to 200MHZ.

5. The value of V_IXis expected to equal 0.5*V_DDQof the transmitting device and must track variations in the dc level of the same.

6. These charactericteristics obey the SSTL-2 class II standards.

URL : www.hbe.co.kr

REV 1.0 (JUNE.2003)

HANBit Electronics Co.,Ltd.

1 2 3 456 7 8...10

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与HDD32M72D9RPW相关器件

型号	品牌	描述	获取价格	数据表
HDD32M72D9RPW-10A	HANBIT	DDR SDRAM Module 256Mbyte (32Mx72bit), based on 32Mx8, 4Banks 8K Ref., 184Pin-DIMM with PL	获取价格
HDD32M72D9RPW-13A	HANBIT	DDR SDRAM Module 256Mbyte (32Mx72bit), based on 32Mx8, 4Banks 8K Ref., 184Pin-DIMM with PL	获取价格
HDD32M72D9RPW-13B	HANBIT	DDR SDRAM Module 256Mbyte (32Mx72bit), based on 32Mx8, 4Banks 8K Ref., 184Pin-DIMM with PL	获取价格
HDD50-12D05P	ETC	DC-DC CONVERTER 50~60W	获取价格
HDD50-12D05T	ETC	DC-DC CONVERTER 50~60W	获取价格
HDD50-12D05X	ETC	DC-DC CONVERTER 50~60W	获取价格

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