Datasheet > HDD32M72D9RPW

HDD32M72D9RPW

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
HANBIT		动态存储器双倍数据速率
页数	文件大小	规格书
10页	407K
描述
DDR SDRAM Module 256Mbyte (32Mx72bit), based on 32Mx8, 4Banks 8K Ref., 184Pin-DIMM with PLL & Register

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HDD32M72D9RPW 数据手册

HANBit

HDD32M72D9RPW

PIN FUNCTION DESCRIPTION

Name

Input Function

CK and /CK are differential clock inputs. All address and control input signals are

sampled on the positive edge of CK and negative edge of CK. Output (read) data

is referenced to both edges of CK. Internal clock signals are derived from CK/CK.

CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Deactivating the clock provides

PRECHARGE

CK, /CK

Clock

POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE

POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions

except for disabling outputs, which is achieved asynchronously. Input buffers,

excluding CK, CK and CKE are disabled during power-down and self refresh

modes, providing low standby power. CKE will recognizean LVCMOS LOW level

prior to VREF being stable on power-up.

CKE

Clock Enable

/CS enables(registered LOW) and disables(registered HIGH) the command

decoder.

All commands are masked when /CS is registered HIGH. /CS provides for external

bank selection on systems with multiple banks. /CS is considered part of the

command code.

/CS

Chip Select

Address

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA12, Column address : CA0 ~ CA9

BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE

command is being applied.

A0 ~ A12

BA0 ~ BA1 Bank select address

Latches row addresses on the positive going edge of the CLK with /RAS low.

Enables row access & precharge.

/RAS

Row address strobe

Columnaddress strobe

Write enable

Latches column addresses on the positive going edge of the CLK with /CAS low.

Enables column access.

/CAS

Enables write operation and row precharge.

/WE

Latches data in starting from /CAS, /WE active.

Output with read data, input with write data. Edge-aligned with read data, cen-

tered in write data. Used to capture write data.

DQS0 ~ 7

Data Strobe

DM is an input mask signal for write data. Input data is masked when DM is

sampled HIGH along with that input data during a WRITE access. DM is sampled

on both edges of DQS. DM pins include dummy loading internally, to matches the

DQ and DQS load-ing.

DM0~7

Input Data Mask

Data input/output

Data inputs/outputs are multiplexed on the same pins.

DQ0 ~ 63

WP pin is connected to Vcc.

When WP is “high”, EEPROM Programming will be inhibited and the entire

memory will be write-protected.

Write Protection

Supply

DQ Power Supply : +2.5V ± 0.2V.

VDDQ

Power Supply : +2.5V ± 0.2V (device specific).

DQ Ground.

VDD

VSS

Supply

SSTL_2 reference voltage.

VREF

URL : www.hbe.co.kr

REV 1.0 (JUNE.2003)

HANBit Electronics Co.,Ltd.

1 2 345 6 7...10

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与HDD32M72D9RPW相关器件

型号	品牌	描述	获取价格	数据表
HDD32M72D9RPW-10A	HANBIT	DDR SDRAM Module 256Mbyte (32Mx72bit), based on 32Mx8, 4Banks 8K Ref., 184Pin-DIMM with PL	获取价格
HDD32M72D9RPW-13A	HANBIT	DDR SDRAM Module 256Mbyte (32Mx72bit), based on 32Mx8, 4Banks 8K Ref., 184Pin-DIMM with PL	获取价格
HDD32M72D9RPW-13B	HANBIT	DDR SDRAM Module 256Mbyte (32Mx72bit), based on 32Mx8, 4Banks 8K Ref., 184Pin-DIMM with PL	获取价格
HDD50-12D05P	ETC	DC-DC CONVERTER 50~60W	获取价格
HDD50-12D05T	ETC	DC-DC CONVERTER 50~60W	获取价格
HDD50-12D05X	ETC	DC-DC CONVERTER 50~60W	获取价格

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