HANBit
HDD32M72B18RPW
CK to valid DQS-in
DQS-in setup time
tDQSS
tWPRES
tWPREH
0.75
0
1.25
0.75
0
1.25
0.75
0
1.25
tCK
ns
tCK
3
DQS-in hold time
0.25
0.25
0.25
DQS-in falling edge to CK rising-setup
time
tDSS
tDSH
tDQSH
tDQSL
tDSC
tIS
0.2
0.2
0.35
0.35
0.9
1.1
1.1
16
0.2
0.2
0.35
0.35
0.9
0.9
0.9
15
0.2
0.2
0.35
0.35
0.9
0.9
0.9
15
tCK
tCK
tCK
tCK
tCK
ns
DQS-in falling edge to CK rising hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
1.1
1.1
1.1
Address and Control Input setup time
Address and Control Input hold time
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
DQ & DM input pulse width
Power down exit time
tIH
ns
tMRD
tDS
ns
0.6
0.6
2
0.5
0.5
1.75
10
0.5
0.5
1.75
10
ns
tDH
ns
tDIPW
tPDEX
tXSW
tXSA
tXSR
TREF
TQH
TWPST
ns
10
ns
Exit self refresh to write command
Exit self refresh to bank active command
Exit self refresh to read command
Refresh interval time
116
80
95
ns
75
75
ns
200
7.8
0.35
0.25
200
7.8
0.35
0.25
200
7.8
Cycle
us
1
4
Output DQS valid window
0.35
0.25
tCK
tCK
DQS write postamble time
Notes :
1. Maximum burst refresh of 8.
2. tHZQ transitions occurs in the same assess time windows as valid data transitions. These parameters are not
referenced to a specific voltage level, but specify when the device output is no longer driving.
3. The specific requirement is that DQS be valid(High-Low) on or before this CK edge. The case shown(DQS going
from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was
in progress, DQS could be High at this time, depending on tDQSS.
4. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
URL : www.hbe.co.kr
REV 1.0 (August.2002)
9
HANBit Electronics Co.,Ltd.