Datasheet > HDD32M72B9

HDD32M72B9

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
HANBIT		动态存储器双倍数据速率
页数	文件大小	规格书
12页	199K
描述
DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM

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HANBit

HDD32M72B9

DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks,

8K Ref., ECC Unbuffered SO-DIMM

Part No. HDD32M72B9

GENERAL DESCRIPTION

The HDD32M72B9 is a 32M x 72 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory module.

The module consists of nine CMOS 32M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages and 2K

EEPROM in 8-pin TSSOP package on a 200-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the printed

circuit board in parallel for each DDR SDRAM. The HDD32M72B9 is a SO-DIMM(Small Outline Dual in line Memory

Module) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible

on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device

to be useful for a variety of high bandwidth, high performance memory system applications. All module components may be

powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.

FEATURES

• Part Identification

HDD32M72B9 – 16B

HDD32M72B9 – 13A

HDD32M72B9 – 13B

166MHz (CL=2.5)

133MHz (CL=2)

133MHz (CL=2.5)

• 256MB(32Mx64) Unbuffered DDR SO-DIMM based on 32Mx8 DDR SDRSM with ECC

• 2.5V ± 0.2V VDD and VDDQ power supply

• Auto & self refresh capability (8192 Cycles/64ms)

• All input and output are compatible with SSTL_2 interface

• Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock

• All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock

• MRS cycle with address key programs

- Latency (Access from column address) : 2, 2.5

- Burst length : 2, 4, 8

- Burst type : Sequential & Interleave

• Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock

• All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock

• The used device is 8M x 8bit x 4Banks DDR SDRAM

• Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)

• Serial Presence detect with EEPROM

URL : www.hbe.co.kr

REV 1.0 (July. 2003)

HANBit Electronics Co.,Ltd.

12 3 4 5 6 7...12

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HDD32M72B9-13A	HANBIT	DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DI	获取价格
HDD32M72B9-13B	HANBIT	DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DI	获取价格
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