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HD74LS373FP-E PDF预览

HD74LS373FP-E

更新时间: 2024-09-27 13:00:43
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8页 97K
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HD74LS373FP-E 数据手册

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HD74LS373  
Octal D-type Transparent Latches (with three-state outputs)  
REJ03D0482–0200  
Rev.2.00  
Feb.18.2005  
The HD74LS373, 8-bit register features totem-pole three-state outputs designed specifically for driving highly-  
capacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive  
provide this register with the capacity of being connected directly to and driving the bus lines in a bus-organized system  
without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O  
ports, bidirectional bus drivers, and working registers.  
The eight latches are transparent D-type latches meaning that while the enable (G) is high the Q outputs will follow the  
data (D) inputs. When the enable is taken low the output will be latched at the level of the data that was setup.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
PRDP0020AC-B  
(DP-20NEV)  
HD74LS373P  
DILP-20 pin  
P
PRSP0020DD-B  
(FP-20DAV)  
HD74LS373FPEL  
HD74LS373RPEL  
SOP-20 pin (JEITA)  
SOP-20 pin (JEDEC)  
FP  
RP  
EL (2,000 pcs/reel)  
EL (1,000 pcs/reel)  
PRSP0020DC-A  
(FP-20DBV)  
Note: Please consult the sales office for the above package availability.  
Pin Arrangement  
Output  
1
Control  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
2
3
1Q  
1D  
Q
D
Q
D
8Q  
OE  
OE  
G
G
8D  
4
2D  
7D  
D
Q
D
Q
G
OE  
G
OE  
5
2Q  
7Q  
6
3Q  
6Q  
Q
D
Q
D
OE  
OE  
G
G
7
3D  
6D  
8
4D  
5D  
D
Q
D
Q
G
OE  
G
OE  
9
4Q  
5Q  
10  
GND  
Enable G  
(Top view)  
Rev.2.00, Feb.18.2005, page 1 of 7  

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