HD74HC294

更新时间： 2024-11-30 05:35:15

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
10页	123K
描述
Programmable Frequency Divider/Digital Timer

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HD74HC294 数据手册

HD74HC292/HD74HC294

Programmable Frequency Divider/Digital Timer

REJ03D0608–0200

(Previous ADE-205-486)

Rev.2.00

Jan 31, 2006

Description

This device divides the incoming clock frequency by a number (a power of 2) that is preset by the Programming inputs.

It has two Clock inputs, either of which may be used as a clock inhibit. The device also has an active-low Reset, which

initializes the internal flip-flop states. Test Point outputs (TP1, TP2, TP3) are provided with HD74HC292 to facilitate

incoming inspections.

Test Point output is provided with HD74HC294 to facilitate incoming inspections.

Features

•

High Speed Operation: t_pd(Clock to Q) = 16 ns typ (C_L= 50 pF)

High Output Current: Fanout of 10 LSTTL Loads

Wide Operating Voltage: V_CC= 2 to 6 V

Low Input Current: 1 µA max

Low Quiescent Supply Current: I_CC(static) = 4 µA max (Ta = 25°C)

Ordering Information

Package Code

(Previous Code)

Package

Abbreviation

Taping Abbreviation

(Quantity)

Part Name

HD74HC292P

HD74HC294FPEL SOP-16 pin (JEITA)

Package Type

PRDP0016AE-B

(DP-16FV)

DILP-16 pin

—

PRSP0016DH-B

(FP-16DAV)

EL (2,000 pcs/reel)

Note: Please consult the sales office for the above package availability.

Function Table

CLR

CLK1

CLK2

Q Output Mode

Cleared to L

Count

Inhibit

H : high level

low level

Rev.2.00 Jan 31, 2006 page 1 of 9

12 3 4 5 6 7...10

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