HD74HC279T-EL

更新时间： 2024-11-30 13:08:15

品牌	Logo	应用领域
日立 - HITACHI		锁存器
页数	文件大小	规格书
9页	61K
描述
R-S Latch, HC/UH Series, 4-Func, Low Level Triggered, 2-Bit, True Output, CMOS, PDSO16, TTP-16DA

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HD74HC279T-EL 数据手册

HD74HC279

Quad. S–R Latches

Description

The latch is ideally suited for use as temporary stage for binary information processing and input/output

units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is

stored before the indicated steady-state input conditions were established. And when both inputs are low,

output is high, but this high level are uncontinuance, if either of input goes high.

Features

•

High Speed Operation: t_pd(S to Q) = 10 ns typ (C_L= 50 pF)

High Output Current: Fanout of 10 LSTTL Loads

Wide Operating Voltage: V_CC= 2 to 6 V

Low Input Current: 1 µA max

Low Quiescent Supply Current: I_CC(static) = 2 µA max (Ta = 25°C)

Function Table

Input

S*²

Output

Q₀

H*¹

H :

High level

Low level

Q₀:

The level of Q respectively, before the indicated steady-state input conditions were established.

Notes: 1. It is unpredictable, if S or R goes High.

2. As to latches which has two S inputs.

H: Both of S inputs are high.

L: Either or both of S inputs are low.

12 3 4 5 6 7...9

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型号	品牌	获取价格	描述	数据表
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HD74HC27FPEL	RENESAS	获取价格	Triple 3-input NOR Gates
HD74HC27FPEL-E	RENESAS	获取价格	IC,LOGIC GATE,3 3-INPUT NOR,HC-CMOS,SOP,14PIN,PLASTIC
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