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HD74HC125FPEL PDF预览

HD74HC125FPEL

更新时间: 2024-11-16 05:35:11
品牌 Logo 应用领域
瑞萨 - RENESAS
页数 文件大小 规格书
9页 104K
描述
Quad. Bus Buffer Gates (with 3-state outputs)

HD74HC125FPEL 数据手册

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HD74HC125/HD74HC126  
Quad. Bus Buffer Gates (with 3-state outputs)  
REJ03D0565-0200  
(Previous ADE-205-439)  
Rev.2.00  
Oct 11, 2005  
Description  
The HD74HC125, HD74HC126 require the 3-state control input C to be taken high to put the output into the high  
impedance condition, whereas the HD74HC125, HD74HC126 requires the control input to be low to put the output into  
high impedance.  
Features  
High Speed Operation: tpd = 8 ns typ (CL = 50 pF)  
High Output Current: Fanout of 15 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-14 pin  
SOP-14 pin (JEITA)  
HD74HC125P  
PRDP0014AB-B  
(DP-14AV)  
P
HD74HC126P  
HD74HC125FPEL  
HD74HC125FPEL  
PRSP0014DF-B  
(FP-14DAV)  
FP  
RP  
T
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
ELL (2,000 pcs/reel)  
PRSP0014DE-A  
(FP-14DNV)  
HD74HC126RPEL SOP-14 pin (JEDEC)  
HD74HC125TELL  
TSSOP-14 pin  
PTSP0014JA-B  
(TTP-14DV)  
HD74HC126TELL  
Note: Please consult the sales office for the above package availability.  
Function Table  
Inputs  
Output  
Y
C
A
HC125  
HC126  
HC125  
HC126  
H
L
H
H
X
L
Z
L
Z
L
L
L
H
H
H
H :  
L :  
X :  
Z :  
High level  
Low level  
Irrelevant  
Off (high-impedance) state of a 3-state output.  
Rev.2.00, Oct 11, 2005 page 1 of 8  

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