HD74HC112T-EL

更新时间： 2024-10-05 13:08:15

品牌	Logo	应用领域
日立 - HITACHI		触发器
页数	文件大小	规格书
9页	62K
描述
J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, TTP-16DA

阅读下载

中文翻译

获取价格

如果您发现信息不准确，欢迎纠错

HD74HC112T-EL 数据手册

HD74HC112

Dual J-K Flip-Flops (with Preset and Clear)

Description

Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is

edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear

and preset are independent of the clock and accomplished by a low logic level on the corresponding input.

Features

•

High Speed Operation: t_pd(Clock to Q) = 17 ns typ (C_L= 50 pF)

High Output Current: Fanout of 10 LSTTL Loads

Wide Operating Voltage: V_CC= 2 to 6 V

Low Input Current: 1 µA max

Low Quiescent Supply Current: I_CC(static) = 2 µA max (Ta = 25°C)

Function Table

Inputs

Output

Preset

Clear

Clock

H*¹

No Change

Toggle

No Change

Note: 1. Q and Q will remain HIGH as long as Preset and Clear are Low, but Q and Q are unpredictable,

if Preset and Clear go HIGH simultaneously.

12 3 4 5 6 7...9

中文翻译

下载PDF

型号	品牌	获取价格	描述	数据表
HD74HC113	RENESAS	获取价格	Dual J-K Flip-Flops (with Preset)
HD74HC113	HITACHI	获取价格	Dual J-K Flip-Flops (with Preset)
HD74HC113FP	ETC	获取价格	FLIP-FLOP\|DUAL\|J/K TYPE\|HC-CMOS\|SOP\|14PIN\|PLASTIC
HD74HC113FP-E	RENESAS	获取价格	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, FP
HD74HC113FPEL	RENESAS	获取价格	Dual J-K Flip-Flops (with Preset)
HD74HC113FP-EL	RENESAS	获取价格	HC/UH SERIES, J-K FLIP-FLOP, PDSO14, FP-14DA
HD74HC113P	RENESAS	获取价格	Dual J-K Flip-Flops (with Preset)
HD74HC113P-E	RENESAS	获取价格	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, 6.
HD74HC113RP-EL	HITACHI	获取价格	J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output,
HD74HC113T	RENESAS	获取价格	暂无描述