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HD74HC107RPEL-E PDF预览

HD74HC107RPEL-E

更新时间: 2024-10-06 04:28:03
品牌 Logo 应用领域
瑞萨 - RENESAS 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
8页 106K
描述
IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,SOP,14PIN,PLASTIC

HD74HC107RPEL-E 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP, SOP14,.25Reach Compliance Code:compliant
风险等级:5.63JESD-30 代码:R-PDSO-G14
负载电容(CL):50 pF逻辑集成电路类型:J-K FLIP-FLOP
最大频率@ Nom-Sup:24000000 Hz最大I(ol):0.004 A
功能数量:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
电源:2/6 V认证状态:Not Qualified
子类别:FF/Latches表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL触发器类型:NEGATIVE EDGE
Base Number Matches:1

HD74HC107RPEL-E 数据手册

 浏览型号HD74HC107RPEL-E的Datasheet PDF文件第2页浏览型号HD74HC107RPEL-E的Datasheet PDF文件第3页浏览型号HD74HC107RPEL-E的Datasheet PDF文件第4页浏览型号HD74HC107RPEL-E的Datasheet PDF文件第5页浏览型号HD74HC107RPEL-E的Datasheet PDF文件第6页浏览型号HD74HC107RPEL-E的Datasheet PDF文件第7页 
HD74HC107  
Dual J-K Flip-Flops (with Clear)  
REJ03D0559-0200  
(Previous ADE-205-432)  
Rev.2.00  
Oct 06, 2005  
Description  
This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse.  
Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and  
accomplished by a low level on the input.  
Features  
High Speed Operation: tpd (Clock to Q) = 19 ns typ (CL = 50 pF)  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
HD74HC107P  
Package Type  
DILP-14 pin  
PRDP0014AB-B  
(DP-14AV)  
P
PRSP0014DF-B  
(FP-14DAV)  
HD74HC107FPEL SOP-14 pin (JEITA)  
HD74HC107RPEL SOP-14 pin (JEDEC)  
FP  
RP  
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
PRSP0014DE-A  
(FP-14DNV)  
Note: Please consult the sales office for the above package availability.  
Function Table  
Inputs  
Outputs  
Clear  
Clock  
J
X
L
K
X
L
Q
Q
L
X
L
H
H
No change  
L
H
L
H
L
H
L
H
H
H
X
X
X
H
H
H
X
X
X
Toggle  
No change  
No change  
No change  
H
L
H
H
H
H :  
L :  
X :  
High level  
Low level  
Irrelevant  
Rev.2.00, Oct 06, 2005 page 1 of 7  

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