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HD74ALVC162834AT PDF预览

HD74ALVC162834AT

更新时间: 2024-11-19 21:17:23
品牌 Logo 应用领域
日立 - HITACHI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
17页 87K
描述
Bus Driver, ALVC/VCX/A Series, 1-Func, 18-Bit, Inverted Output, CMOS, PDSO56, TSSOP-56

HD74ALVC162834AT 数据手册

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HD74ALVC162834A  
18-bit Universal Bus Driver with 3-state Outputs  
and Inverted Latch Enable  
ADE-205-293B (Z)  
Rev. 2  
Oct. 2001  
Description  
The HD74ALVC162834A is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation.  
Data flow from A to Y is controlled by the output enable (OE). The device operates in the transparent mode  
when the latch enable (LE) is low. When LE is low, the A data is latched if the clock (CLK) input is held  
at a high or low logic level. If the LE is high, the A data is stored in the latch/flip flop on the low to high  
transition of CLK. When OE is high, the outputs are in the high impedance state.  
To ensure the high impedance state during power up or power down, OE should be tied to VCC through a  
pullup registor; the minimum value of the registor is determined by the current sinking capability of the  
driver.  
All outputs, which are designed to sink up to 12 mA, include series dumping resistors to reduce overshoot  
and undershoot.  
Features  
Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 1.1”  
CC = 2.3 V to 3.6 V  
V
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)  
Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)  
High output current ±12 mA (@VCC = 3.0 V)  
All outputs have series dumping resistors, so no external resistors are required  
tpd (CLK to Y) = 3.5 ns (Max) (@VCC = 3.3±0.3 V, CL = 50 pF, Ta = 0 to 85°C)  
tpd (CLK to Y) = 2.5 ns (Max) (@VCC = 3.3±0.3 V, CL = 30 pF, Ta = 0 to 85°C)  
Package type  
Package type  
TSSOP-56pin  
TVSOP-56pin  
Package code  
TTP-56DAV  
TTP-56DBV  
Package suffix  
Taping code  
T
EL(1000pcs / Reel)  
EL(1000pcs / Reel)  
N

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