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HD74ALVC162835T PDF预览

HD74ALVC162835T

更新时间: 2024-11-19 13:01:27
品牌 Logo 应用领域
日立 - HITACHI 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
15页 66K
描述
Bus Driver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56

HD74ALVC162835T 数据手册

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HD74ALVC162835  
18-bit Universal Bus Driver with 3-state Outputs  
ADE-205-201E (Z)  
Preliminary  
6th. Edition  
January 1999  
Description  
The HD74ALVC162835 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation.  
Data flow from A to Y is controlled by the output enable (OE). The device operates in the transparent mode  
when the latch enable (LE) is high. When LE is low, the A data is latched if the clock (CLK) input is held  
at a high or low logic level. If the LE is low, the A data is stored in the latch/flip flop on the low to high  
transition of CLK. When OE is high, the outputs are in the high impedance state.  
To ensure the high impedance state during power up or power down, OE should be tied to VCC through a  
pullup registor; the minimum value of the registor is determined by the current sinking capability of the  
driver.  
All outputs, which are designed to sink up to 12 mA, include 26 resistors to reduce overshoot and  
undershoot.  
Features  
Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”  
VCC = 2.3 V to 3.6 V  
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)  
Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)  
High output current ±12 mA (@VCC = 3.0 V)  
All outputs have equivalent 26 series resistors, so no external resistors are required  

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