HD74AC107RP-EL

更新时间： 2024-12-01 13:08:15

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HD74AC107RP-EL 数据手册

HD74AC107/HD74ACT107

Dual JK Flip-Flop (with Separate Clear and Clock)

Description

The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop.

Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the

coupling transistors which connect the master and slave sections. The sequence of operation is as follows:

1) isolate slave from master; 2) enter information from J and K inputs to master; 3) disable J and K inputs;

4) transfer information from master to slave.

Features

•

Outputs Source/Sink 24 mA

HD74ACT107 has TTL-Compatible Inputs

Pin Arrangement

J₁

K₁

Q₂

14 V_CC

13 C_D1

12 CP₁

11 K₂

10 C_D2

CP₂

GND 7

J₂

(Top view)

12 3 4 5 6 7...10

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型号	品牌	获取价格	描述	数据表
HD74AC107RPVEL	RENESAS	获取价格	暂无描述
HD74AC107T	RENESAS	获取价格	J-K FLIP-FLOP, PDSO14, TTP-14D
HD74AC107T	HITACHI	获取价格	J-K Flip-Flop, AC Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CM
HD74AC107T-EL	RENESAS	获取价格	J-K FLIP-FLOP, PDSO14, TTP-14D
HD74AC107T-EL	HITACHI	获取价格	暂无描述
HD74AC109FP	ETC	获取价格	J-K-Type Flip-Flop
HD74AC109P	ETC	获取价格	J-K-Type Flip-Flop
HD74AC10FP	ETC	获取价格	Triple 3-input NAND Gate
HD74AC10P	ETC	获取价格	Triple 3-input NAND Gate
HD74AC112	HITACHI	获取价格	Dual JK Negative Edge-Triggered Flip-Flop