5秒后页面跳转
HD49351BP PDF预览

HD49351BP

更新时间: 2024-02-09 20:32:16
品牌 Logo 应用领域
瑞萨 - RENESAS 转换器
页数 文件大小 规格书
29页 330K
描述
CDS/PGA & 10-bit A/D TG Converter

HD49351BP 技术参数

生命周期:Transferred零件包装代码:BGA
包装说明:FBGA-65针数:65
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.65
Is Samacsys:N最大模拟输入电压:3 V
转换器类型:ADC, PROPRIETARY METHODJESD-30 代码:S-XBGA-B65
JESD-609代码:e1长度:6 mm
模拟输入通道数量:1位数:10
功能数量:1端子数量:65
最高工作温度:75 °C最低工作温度:-10 °C
输出位码:BINARY输出格式:PARALLEL, WORD
封装主体材料:UNSPECIFIED封装代码:TFBGA
封装等效代码:BGA64,10X10,20封装形状:SQUARE
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH电源:3 V
认证状态:Not Qualified采样并保持/跟踪并保持:SAMPLE
座面最大高度:1.2 mm子类别:Other Converters
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL EXTENDED
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:0.5 mm端子位置:BOTTOM
宽度:6 mmBase Number Matches:1

HD49351BP 数据手册

 浏览型号HD49351BP的Datasheet PDF文件第1页浏览型号HD49351BP的Datasheet PDF文件第3页浏览型号HD49351BP的Datasheet PDF文件第4页浏览型号HD49351BP的Datasheet PDF文件第5页浏览型号HD49351BP的Datasheet PDF文件第6页浏览型号HD49351BP的Datasheet PDF文件第7页 
HD49351BP/HBP  
Pin Arrangement  
10  
9
8
7
6
5
4
3
2
1
32  
31  
30  
29  
26  
24  
22  
19  
17  
16  
A
B
C
D
E
F
XV3 XV2 XV1 DVdd3 H2 DVss4 H1 RG VD_i/o HD_i/o  
33 34 28 27 25 23 21 20 18 15  
XV4 CH1 DVdd4 1/4clk DVss4 1/2clk DVdd4 DVdd3 Reset CLK_in  
35 36 14 14 13  
CH2 CH3  
DVss3 DVss3 DVdd2  
38 37  
XSUB CH4  
40 39  
12  
D9  
11  
D8  
10  
D7  
8
D5  
SUB_PD SUB_SW  
42  
41  
9
D6  
6
D3  
DVss3 Strob  
45 43  
Bias AVss  
7
D4  
4
D1  
G
H
J
46 44  
VRB ADC_in  
5
D2  
3
D0  
48  
49  
52  
55  
56  
57  
59  
61  
62  
2
VRM AVdd AVdd AVss test2 test1 DVdd1 41cont CDS_CS DVss1,2  
47 50 51 53 54 58 60 63 64  
VRT BLKC CDS_in BLKFB BLKSH DLLC MON Sdata SCK ID  
1
K
(Top view)  
Notes: 1. Pin 41 outputs the STROB, pin 39 outputs the SUB_SW when pin 61 is Low.  
2. Pin 41 inputs the Vgate, pin 39 inputs the ADCK when pin 61 is High.  
3. 1/2 and 4clk output terminal becomes 1/3 and 1/6clk output respectively,  
when operating TG in 3 divided mode.  
Pin Description  
BGA  
PAD  
No.  
Analog(A) or  
I/O Digital(D)  
Pin No.  
Symbol  
ID  
Description  
Remarks  
K1  
J1  
1
2
Odd/even number line detecting pulse output pin  
CDS Digital ground + ADC output buffer ground (0V)  
Digital output (D0; LSB, D9; MSB)  
ADC output buffer power supply (3 V)  
General ground for TG (0V)  
O
O
I
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
2 mA/10 pF  
DVss1, 2  
D0 to D9  
DVdd2  
Dvss3  
CLK_in  
HD_in  
VD_in  
Reset  
RG  
H1 to D2 3 to 12  
2 mA/10 pF  
C1  
C2, C3  
B1  
A1  
A2  
B2  
A3  
B3  
B4  
A4  
B5  
A5  
B6  
A6  
B7  
B8  
A7  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
CLK input (max 72 MHz)  
HD input  
I
VD input  
I
Hardware reset (for DLL reset)  
Reset gate pulse output  
I
Schmitt trigger  
3 mA/10 pF  
O
O
O
O
O
DVdd3  
DVdd4  
H1  
General power supply for TG (3V)  
H1,2 buffer power supply (3 V)  
H.CCD transfer pulse output-1  
CLK_in 2 divided output. 3 divided output at 3 divided mode  
H1,2 buffer ground (0 V)  
30 mA/165 pF  
2 mA/10 pF  
1/2clk_o  
Dvss4  
Dvss4  
H2  
H1,2 buffer ground (0 V)  
H.CCD transfer pulse output-2  
CLK_in 4 divided output. 6 divided output at 3 divided mode  
H1,2 buffer power supply (3 V)  
General power supply for TG (3 V)  
30 mA/165 pF  
2 mA/10 pF  
1/4clk_o  
DVdd4  
DVdd3  
Rev.1.0, Jul 06, 2004, page 2 of 28  

与HD49351BP相关器件

型号 品牌 描述 获取价格 数据表
HD49351BP-E RENESAS 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, BGA65, FBGA-65

获取价格

HD49351HBP RENESAS CDS/PGA & 10-bit A/D TG Converter

获取价格

HD49404 ETC TV/Video Signal Processor

获取价格

HD49405 ETC

获取价格

HD49406 ETC MEMORY CONTROLLER

获取价格

HD49409FS ETC Picture-in-Picture Circuit

获取价格