Datasheet > HD125L15J

HD125L15J

更新时间： 2024-09-22 09:34:47

品牌	Logo	应用领域
联笙电子 - AMICC		静态存储器
页数	文件大小	规格书
16页	258K
描述
SRAM

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数据手册

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HD125L15J 数据手册

HD121/125

ADP SRAM I

5 Volt x8 Asynchronous Dual-Port Static RAM

Memory Configuration

Mode

Master

Slave

Device

HD121L

HD125L

2K x 9

Key Features:

•

Industry leading asynchronous Dual-Port Static RAM (up to 15ns)

Simultaneous memory access through two ports

TTL compatible; 5V power supply

Supports Interrupt arbitration schemes

Bus Width can easily expand to over 18 bits by using both MASTER and SLAVE

HD121 with on-chip port arbitration logic

BUSY output flag on HD121; BUSY input flag on HD125

Available packages: 52 – pin Plastic Lead Chip Carrier (PLCC)

(0^°C to 70^°C) Commercial operating temperature available for access time of 15ns and above

(-40^°C to 85^°C) Industrial operating temperature available for access time of 25ns

Pin-to-pin compatible with conventional dual-port devices including IDT 70121, 70125

Product Description:

HBA’s Asynchronous Dual-Port (ADP I) Static RAM offers industry leading 0.25um process technology and 2K x 9 memory

configuration. Both devices support two memory ports with independent control, address, and I/O pins that enable simultaneous,

asynchronous access to any location in memory. System designer has full flexibility of implementing deeper and wider memory

using the depth and width expansion features.

The HD121 is a stand alone 18K-bit Dual-Port Static RAM or as a “MASTER” Dual-Port Static RAM with HD125 as a

“SLAVE” Dual-Port Static RAM in 18-bit-or-more bus width application. No additional discrete logic is required when using the

MASTER/SLAVE configuration to provide bus width expansion.

These devices have low power consumption, hence minimizing system power requirements. They are ideal for applications such

as data communication, telecommunication, multiprocessing, test equipment, network switching, etc.

PRELIMINARY

5HD091A

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