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HCF4043BC1 PDF预览

HCF4043BC1

更新时间: 2024-11-18 22:34:03
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路
页数 文件大小 规格书
13页 304K
描述
QUAD 3-STATE R-S LATCHES

HCF4043BC1 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:PLASTIC, LCC-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.74Is Samacsys:N
系列:4000/14000/40000JESD-30 代码:S-PQCC-J20
JESD-609代码:e3长度:8.9662 mm
负载电容(CL):50 pF逻辑集成电路类型:R-S LATCH
位数:4功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC20,.4SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:3/15 V
Prop。Delay @ Nom-Sup:300 ns传播延迟(tpd):300 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:FF/Latches最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:HIGH LEVEL宽度:8.9662 mm
Base Number Matches:1

HCF4043BC1 数据手册

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HCC/HCF4043B  
HCC/HCF4044B  
QUAD 3-STATE R-S LATCHES  
QUAD NOR  
R-S LATCH-4043B  
R-S LATCH-4044B  
QUAD NAND  
.
.
.
QUIESCENT CURRENT SPECIFIED TO 20V  
FOR HCC DEVICE  
3-LEVEL OUTPUTS WITH COMMON OUTPUT  
ENABLE  
EY  
F
(Plastic Package)  
(Ceramic Frit Seal Package)  
SEPARATE SET AND RESET INPUT FOR  
EACH LATCH  
5V, 10V, AND 15V PARAMETRIC RATINGS  
NOR AND NAND CONFIGURATIONS  
INPUT CURRENT OF 100nA AT 18V AND 25°C  
FOR HCC DEVICE  
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVESTANDARDN°13A, ”STANDARD SPE-  
CIFICATIONS FOR DESCRIPTION OF ”B”  
SERIES CMOS DEVICES”  
.
.
.
M1  
C1  
.
.
(Micro Package)  
(Plastic Chip Carrier)  
ORDER CODES :  
HCC40XXBF  
HCF40XXBEY  
HCF40XXBM1  
HCF40XXBC1  
PIN CONNECTIONS  
4043B  
DESCRIPTION  
The HCC4043B, HCC4044B, (extended tempera-  
ture range) and the HCF4043B, HCF4044B (inter-  
mediate temperature range) are monolithic  
integrated circuits, available in 16-lead dual in-line  
plastic or ceramic package and plastic micropack-  
age. The HCC/HCF4043B types are quad cross-  
coupled 3-state COS/MOS NOR latches and the  
HCC/HCF4044B types are quad cross-coupled 3-  
state COS/MOS NAND latches. Each latch has a  
separate Q output and individual SET and RESET  
inputs. The Q outputs are controlled by a common  
ENABLE input. A logic ”1” or ”high” on the ENABLE  
input connects the latch states to the Q outputs. A  
logic ”0” or ”low” on the ENABLE input disconnects  
the latch states from the Q outputs, resulting in an  
open circuit condition on the Q outputs. The open  
circuit feature allows common bussing of the out-  
puts.  
4044B  
June 1989  
1/13  

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