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HC49 PDF预览

HC49

更新时间: 2024-11-20 22:33:15
品牌 Logo 应用领域
日立 - HITACHI 计数器
页数 文件大小 规格书
8页 46K
描述
Dual 4-bit Decade Counters

HC49 数据手册

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HD74HC490  
Dual 4-bit Decade Counters  
Description  
This circuit contains eight master-slave flip-flops and additional gating to implement two individual 4-bit  
decade counters. Each decade counter has individual clock, clear and set-to-9 inputs. BCD count  
sequences of any length up to divide-by-100 may be implemented with a single HD74HC490. Buffering  
on each output is provided to ensure that suceptibility to collector communication is reduced significantly.  
The counters have paralle outputs from each counter state so that submultiples of the input count frequency  
are available for system timing signals.  
Features  
High Speed Operation: tpd (Clock to QA) = 13 ns typ (CL = 50 pF)  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  
Function Table  
Clear/Set-To-9  
Inputs  
Outputs  
Clear  
Set-To-9  
QA  
L
QB  
L
QC  
L
QD  
L
H
L
L
L
H
L
H
L
L
H
Count  

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